DS21455 데이터 시트보기 (PDF) - Maxim Integrated

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DS21455

Quad T1/E1/J1 Transceivers

Maxim Integrated 

DS21455/DS21458 Quad T1/E1/J1 Transceivers

24.5.1 Receive Section ............................................................................................................155

24.5.2 Transmit Section ...........................................................................................................157

24.6 D4/SLC-96 OPERATION .................................................................................................. 157

25. LINE INTERFACE UNIT (LIU) ................................................................................................................... 158

25.1 LIU OPERATION .............................................................................................................. 159

25.2 LIU RECEIVER................................................................................................................. 159

25.2.1 Receive Level Indicator................................................................................................160

25.2.2 Receive G.703 Section 10 Synchronization Signal .................................................160

25.2.3 Monitor Mode.................................................................................................................160

25.3 LIU TRANSMITTER ........................................................................................................... 161

25.3.1 Transmit Short-Circuit Detector/Limiter .....................................................................161

25.3.2 Transmit Open-Circuit Detector ..................................................................................161

25.3.3 Transmit BPV Error Insertion ......................................................................................162

25.3.4 Transmit G.703 Section 10 Synchronization Signal (E1 Mode).............................162

25.4 MCLK PRESCALER.......................................................................................................... 162

25.5 JITTER ATTENUATOR ....................................................................................................... 162

25.6 CMI (CODE MARK INVERSION) OPTION ............................................................................ 163

25.7 LIU CONTROL REGISTERS ............................................................................................... 164

25.8 RECOMMENDED CIRCUITS................................................................................................ 173

25.9 COMPONENT SPECIFICATIONS.......................................................................................... 175

26. PROGRAMMABLE IN-BAND LOOP CODE GENERATION AND DETECTION ..................................... 179

27. BERT FUNCTION ...................................................................................................................................... 186

27.1 BERT REGISTER DESCRIPTION........................................................................................ 187

27.2 BERT REPETITIVE PATTERN SET..................................................................................... 192

27.3 BERT BIT COUNTER ....................................................................................................... 193

27.4 BERT ERROR COUNTER ................................................................................................. 194

28. PAYLOAD ERROR INSERTION FUNCTION ........................................................................................... 195

28.1 NUMBER OF ERROR REGISTERS....................................................................................... 197

28.1.1 Number of Errors Left Register...................................................................................198

29. INTERLEAVED PCM BUS OPERATION .................................................................................................. 199

29.1 CHANNEL INTERLEAVE MODE ........................................................................................... 199

29.2 FRAME INTERLEAVE MODE............................................................................................... 199

30. EXTENDED SYSTEM INFORMATION BUS (ESIB) ................................................................................. 202

31. PROGRAMMABLE BACKPLANE CLOCK SYNTHESIZER .................................................................... 208

32. FRACTIONAL T1/E1 SUPPORT ............................................................................................................... 209

33. USER-PROGRAMMABLE OUTPUT PINS ............................................................................................... 210

34. TRANSMIT FLOW DIAGRAMS................................................................................................................. 211

35. JTAG-BOUNDARY-SCAN ARCHITECTURE AND TEST-ACCESS PORT ............................................ 216

35.1 INSTRUCTION REGISTER .................................................................................................. 220

35.2 TEST REGISTERS............................................................................................................. 222

35.3 BOUNDARY SCAN REGISTER ............................................................................................ 222

35.4 BYPASS REGISTER .......................................................................................................... 222

35.5 IDENTIFICATION REGISTER ............................................................................................... 222

36. FUNCTIONAL TIMING DIAGRAMS.......................................................................................................... 228

36.1 T1 MODE ........................................................................................................................ 228

36.2 E1 MODE ........................................................................................................................ 238

37. OPERATING PARAMETERS.................................................................................................................... 251

38. AC TIMING PARAMETERS AND DIAGRAMS......................................................................................... 253

38.1 MULTIPLEXED BUS AC CHARACTERISTICS ........................................................................ 253

38.2 NONMULTIPLEXED BUS AC CHARACTERISTICS.................................................................. 256

38.3 RECEIVE SIDE AC CHARACTERISTICS............................................................................... 259

38.4 TRANSMIT AC CHARACTERISTICS..................................................................................... 265

39. PACKAGE INFORMATION ....................................................................................................................... 269

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