DS2450 데이터 시트보기 (PDF) - Maxim Integrated

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DS2450

1-Wire Quad A/D Converter

Maxim Integrated 

DS2450

With VCC power supply the bus master may either send a reset pulse to exit the Convert command or

continuously generate read data time slots. As long as the DS2450 is busy with conversions the bus

master will read 0’s. After the conversion is completed the bus master will receive 1’s instead. Since in a

open-drain environment a single 0 overwrites multiple 1’s the bus master can monitor multiple devices

converting simultaneously and immediately knows when the last one is ready. As in the parasitically

powered scenario the bus master finally has to exit the Convert command by issuing a rest pulse.

1-WIRE BUS SYSTEM

The 1-Wire bus is a system which has a single bus master and one or more slaves. In all instances the

DS2450 is a slave device. The discussion of this bus system is broken down into three topics: hardware

configuration, transaction sequence, and 1-Wire signaling (signal types and timing). A 1-Wire protocol

defines bus transactions in terms of the bus state during specific time slots that are initiated on the falling

edge of sync pulses from the bus master. For a more detailed protocol description, refer to Chapter 4 of

the Book of DS19xx iButton Standards.

HARDWARE CONFIGURATION

The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to

drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open

drain or 3-state outputs. The 1-Wire port of the DS2450 is open drain with an internal circuit equivalent

to that shown in Figure 8. A multidrop bus consists of a 1-Wire bus with multiple slaves attached. At

regular speed the 1-Wire bus has a maximum data rate of 16.3k bits per second. The speed can be

boosted to 142k bits per second by activating the Overdrive Mode. The 1-Wire bus requires a pullup

resistor of approximately 5kΩ at regular speed or maximum 2.2kΩ at Overdrive speed for

communication. During A/D conversions the bus master must provide a strong pullup to 5V to supply

sufficient energy if the DS2450 is powered entirely from the 1-Wire bus.

The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus

MUST be left in the idle state if the transaction is to resume. If this does not occur and the bus is left low

for more than 16 μs (Overdrive Speed) or more than 120 μs (regular speed), one or more devices on the

bus may be reset.

HARDWARE CONFIGURATION Figure 8

SEE TEXT

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