ISL12023 데이터 시트보기 (PDF) - Renesas Electronics
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ISL12023
Renesas Electronics
ISL12023 Datasheet PDF : 29 Pages
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ISL12023
Brownout Detection
The ISL12023 monitors the VDD level continuously and provides
warning if the VDD level drops below prescribed levels. There are
six (6) levels that can be selected for the trip level. These values
are 85% below popular VDD levels. The LVDD bit in the Status
Register will be set to “1” when brownout is detected. Note that
the I2C serial bus remains active unless the Battery VTRIP levels
are reached. The LVRST output becomes active (LOW) when the
Power Brownout Bit (LVDD) is set.
When the VDD power is re-established and is above the 85% VDD
+ 50mV trip point, the LVRST output is set HIGH. The LVDD bit is
reset once it is read by the Micro. Note that the I2C serial bus
remains active unless the Battery VTRIP levels are reached.
Battery Level Monitor
The ISL12023 has a built in warning feature once the backup
battery level drops first to 85% and then to 75% of the battery’s
nominal VBAT level. When the battery voltage drops to between
85% and 75%, the LBAT85 bit is set in the status register. When
the level drops below 75%, both LBAT85 and LBAT75 bits are set
in the status register.
The battery level monitor is not functional in battery backup
mode. In order to read the monitor bits after powering up VDD,
instigate a battery level measurement by setting the TSE bit to
"1" (BETA register), and then read the bits.
There is a Battery Time Stamp Function available. Once the VDD
is low enough to enable switchover to the battery, the RTC
time/date are written into the TSV2B register. This information
can be read from the TSV2B registers to discover the point in
time of the VDD power-down. If there are multiple power-down
cycles before reading these registers, the first values stored in
these registers will be retained. These registers will hold the
original power-down value until they are cleared by setting CLRTS
= 1 to clear the registers.
The normal power switching of the ISL12023 is designed to
switch into battery-backup mode only if the VDD power is lost.
This will ensure that the device can accept a wide range of
backup voltages from many types of sources while reliably
switching into backup mode.
Note that the ISL12023 is not guaranteed to operate with VBAT <
1.8V. If the battery voltage is expected to drop lower than this
minimum, correct operation of the device, especially after a VDD
power down cycle, is not guaranteed.
The minimum VBAT to insure SRAM is stable is 1.0V. Below that,
the SRAM may be corrupted when VDD power resumes.
Real Time Clock Operation
The Real Time Clock (RTC) uses an external 32.768kHz quartz
crystal to maintain an accurate internal representation of
second, minute, hour, day of week, date, month, and year. The
RTC also has leap-year correction. The clock also corrects for
months having fewer than 31 days and has a bit that controls 24-
hour or AM/PM format. When the ISL12023 powers up after the
loss of both VDD and VBAT, the clock will not begin incrementing
until at least one byte is written to the clock register.
Single Event and Interrupt
The alarm mode is enabled via the MSB bit. Choosing single
event or interrupt alarm mode is selected via the IM bit. Note that
when the frequency output function is enabled, the alarm
function is disabled.
The standard alarm allows for alarms of time, date, day of the
week, month, and year. When a time alarm occurs in single
event mode, an IRQ pin will be pulled low and the alarm status
bit (ALM) will be set to “1”.
The pulsed interrupt mode allows for repetitive or recurring alarm
functionality. Hence, once the alarm is set, the device will
continue to alarm for each occurring match of the alarm and
present time. Thus, it will alarm as often as every minute (if only
the nth second is set) or as infrequently as once a year (if at least
the nth month is set). During pulsed interrupt mode, the IRQ pin
will be pulled low for 250ms and the alarm status bit (ALM) will
be set to “1”.
The ALM bit can be reset by the user or cleared automatically
using the auto reset mode (see ARST bit). The alarm function can
be enabled/disabled during battery-backup mode using the
FOBATB bit. For more information on the alarm, please see
“ALARM Registers (10h to 15h)” on page 18.
Frequency Output Mode
The ISL12023 has the option to provide a clock output signal
using the FOUT open drain output pin. The frequency output mode
is set by using the FO bits to select one of 15 possible output
frequency values from 1/32Hz to 32kHz. The frequency output
can be enabled/disabled during battery-backup mode using the
FOBATB bit.
General Purpose User SRAM
The ISL12023 provides 128 bytes of user SRAM. The SRAM will
continue to operate in battery-backup mode. However, it should
be noted that the I2C bus is disabled in battery-backup mode.
I2C Serial Interface
The ISL12023 has an I2C serial bus interface that provides
access to the control and status registers and the user SRAM.
The I2C serial interface is compatible with other industry I2C
serial bus protocols using a bi-directional data signal (SDA) and a
clock signal (SCL).
Oscillator Compensation
The ISL12023 provides both initial timing correction and
temperature correction due to variation of the crystal oscillator.
Analog and digital trimming control is provided for initial
adjustment, and a temperature compensation function is
provided to automatically correct for temperature drift of the
crystal. Initial values are preset and recalled on initial power-up
for the Initial AT and DT settings (IATR, IDTR), temperature
coefficient (ALPHA), crystal capacitance (BETA), and the crystal
turnover temperature (XTO). These initial values are typical of
units available on the market, although the user may program
specific values after testing for best accuracy. The function can
be enabled/disabled at any time and can be used in battery
mode as well.
FN6682 Rev 3.00
December 6, 2011
Page 10 of 29
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