ISL12023 데이터 시트보기 (PDF) - Renesas Electronics
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ISL12023
Renesas Electronics
ISL12023 Datasheet PDF : 29 Pages
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ISL12023
Typical Performance Curves Temperature is +25°C unless otherwise specified. (Continued)
110
100
90
VDD = 5.5V
80
VBAT = 2.7V
70
60
VDD = 3.3V
50
40-40
-20
0
20
40
60
80
TEMPERATURE (°C)
FIGURE 8. IDD WITH TSE = 1 vs TEMPERATURE
110
100
90
80
VBAT = 5.5V
70
60
VBAT = 3.0V
50
VBAT = 1.8V
40
30
20 -40
-20
0
20
40
60
80
TEMPERATURE (°C)
FIGURE 9. IBAT with TSE = 1, BTSE = 1 vs TEMPERATURE
General Description
The ISL12023 device is a low power real time clock (RTC) with
embedded temperature sensors. It contains crystal frequency
compensation circuitry over the operating temperature range,
clock/calendar, power fail and low battery monitors, brownout
indicator with separate low voltage reset pin (LVRST), 1 periodic or
polled alarm, intelligent battery-backup switching and 128 Bytes of
battery-backed user SRAM.
The oscillator uses an external, low cost 32.768kHz crystal. The
real time clock tracks time with separate registers for hours,
minutes and seconds. The device has calendar registers for date,
month, year and day of the week. The calendar is accurate
through 2099, with automatic leap year correction. In addition,
the ISL12023 could be programmed for automatic Daylight
Savings Time (DST) adjustment by entering local DST
information.
The ISL12023’s alarm can be set to any clock/calendar value for
a match. For example, every minute, every Tuesday or at 5:23
a.m. on March 21. The alarm status is available by checking the
Status Register, or the device can be configured to provide a
hardware interrupt via the IRQ pin. There is a repeat mode for the
alarm allowing a periodic interrupt every minute, every hour,
every day, etc.
The device also offers a backup power input pin. This VBAT pin
allows the device to be backed up by battery or super capacitor
with automatic switchover from VDD to VBAT. The ISL12023
device is specified for VDD = 2.7V to 5.5V and the clock/calendar
portion of the device remains fully operational in battery-backup
mode down to 1.8V (Standby Mode). The VBAT level is monitored
and reported against preselected levels. The first report is
registered when the VBAT level falls below 85% of nominal level,
the second level is set for 75%. Battery levels are stored in
PWR_VBAT registers.
The ISL12023 offers a “Brownout” alarm once the VDD falls
below a pre-selected trip level. This allows system Micro to save
vital information to memory before complete power loss. There
are six VDD levels that could be selected for initiation of the
Brownout alarm.
Pin Descriptions
X1, X2
The X1 and X2 pins are the input and output, respectively, of an
inverting amplifier. An external 32.768kHz quartz crystal is used
with the device to supply a timebase for the real time clock.
Internal compensation circuitry with internal temperature sensor
provides frequency corrections for selected popular crystals to
±5ppm over the operating temperature range from -40°C to
+85°C (see “Application Section” on page 24 for recommended
crystal). The ISL12023 allows the user to input via I2C serial bus
the temperature variation profile of an individual crystal. The
oscillator compensation network can also be used to calibrate
the initial crystal timing accuracy to less than 1ppm error at
room temperature. The device can also be driven directly from a
32.768kHz source at pin X1.
X1
X2
FIGURE 10. RECOMMENDED CRYSTAL CONNECTION
VBAT
This input provides a backup supply voltage to the device. VBAT
supplies power to the device in the event that the VDD supply
fails. The device will automatically switch to the VBAT input when
VDD drops below a prescribed level. See the Battery Monitor
parameter in the electrical spec table titled “DC Operating
Characteristics-RTC” on page 3. This pin can be connected to a
battery, a super capacitor or tied to ground if not used.
IRQ (Interrupt Output)
This pin provides an interrupt signal output. This signal notifies a
host processor that an alarm has occurred and requests action. It
is an open drain active low output. Once triggered, the output will
stay low until the Alarm status register bit is reset or, if the auto
reset function is used, a read is performed to the status register.
FN6682 Rev 3.00
December 6, 2011
Page 8 of 29
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