74VHCT02-Q100(2020) 데이터 시트보기 (PDF) - Nexperia B.V. All rights reserved
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74VHCT02-Q100 Datasheet PDF : 12 Pages
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Nexperia
74VHC02-Q100; 74VHCT02-Q100
Quad 2-input NOR gate
12. Abbreviations
Table 10. Abbreviations
Acronym
CMOS
DUT
ESD
HBM
LSTTL
MIL
MM
TTL
Description
Complementary Metal-Oxide Semiconductor
Device Under Test
ElectroStatic Discharge
Human Body Model
Low-power Schottky Transistor-Transistor Logic
Military
Machine Model
Transistor-Transistor Logic
13. Revision history
Table 11. Revision history
Document ID
74VHC_VHCT02_Q100 v.2
Modifications:
74VHC_VHCT02_Q100 v.1
Release date Data sheet status
20200415
Product data sheet
Change notice Supersedes
-
74VHC_VHCT02_Q100 v.1
• The format of this data sheet has been redesigned to comply with the identity guidelines
of Nexperia.
• Legal texts have been adapted to the new company name where appropriate.
• Section 2 updated.
• Table 4: Derating values for Ptot total power dissipation have changed.
• Package outline drawing SOT762-1 (DHVQFN14) updated.
20131115
Product data sheet
-
-
74VHC_VHCT02_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 15 April 2020
© Nexperia B.V. 2020. All rights reserved
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