74VHCT02D-Q100(2020) 데이터 시트보기 (PDF) - Nexperia B.V. All rights reserved
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74VHCT02D-Q100 Datasheet PDF : 12 Pages
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Nexperia
74VHC02-Q100; 74VHCT02-Q100
Quad 2-input NOR gate
4. Functional diagram
2 1A
3 1B
5 2A
6 2B
8 3A
9 3B
11 4A
12 4B
1Y 1
2Y 4
3Y 10
4Y 13
mna216
Fig. 1. Logic symbol
2
≥1
3
1
5
≥1
6
4
8
≥1
9
10
11
≥1
12
13
001aah084
Fig. 2. IEC logic symbol
A
Y
B
mna215
Fig. 3. Logic diagram (one gate)
5. Pinning information
5.1. Pinning
74VHC02-Q100
74VHCT02-Q100
1Y 1
1A 2
1B 3
2Y 4
2A 5
2B 6
GND 7
14 VCC
13 4Y
12 4B
11 4A
10 3Y
9 3B
8 3A
aaa-009473
Fig. 4. Pin configuration SOT108-1 (SO14) and
SOT402-1 (TSSOP14)
74VHC02-Q100
74VHCT02-Q100
terminal 1
index area
1A 2
1B 3
2Y 4
2A 5
2B 6
GND(1)
13 4Y
12 4B
11 4A
10 3Y
9 3B
aaa-009475
Transparent top view
(1) This is not a ground pin. There is no electrical or
mechanical requirement to solder the pad. In case
soldered, the solder land should remain floating or
connected to GND.
Fig. 5. Pin configuration SOT762-1 (DHVQFN14)
5.2. Pin description
Table 2. Pin description
Symbol
1Y, 2Y, 3Y, 4Y
1A, 2A, 3A, 4A
1B, 2B, 3B, 4B
GND
VCC
Pin
1, 4, 10, 13
2, 5, 8, 11
3, 6, 9, 12
7
14
Description
data output
data input
data input
ground (0 V)
supply voltage
74VHC_VHCT02_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 15 April 2020
© Nexperia B.V. 2020. All rights reserved
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