ISL6431 데이터 시트보기 (PDF) - Renesas Electronics

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ISL6431

Advanced Pulse Width Modulation (PWM) Controller for Broadband Applications

Renesas Electronics 

ISL6431

ISL6431

Input Capacitor Selection

Use a mix of input bypass capacitors to control the voltage

overshoot across the MOSFETs. Use small ceramic

capacitors for high frequency decoupling and bulk capacitors

to supply the current needed each time Q1 turns on. Place

the small ceramic capacitors physically close to the

MOSFETs and between the drain of Q1 and the source of Q2.

The important parameters for the bulk input capacitor are the

voltage rating and the RMS current rating. For reliable

operation, select the bulk capacitor with voltage and current

ratings above the maximum input voltage and largest RMS

current required by the circuit. The capacitor voltage rating

should be at least 1.25 times greater than the maximum input

voltage and a voltage rating of 1.5 times is a conservative

guideline. The RMS current rating requirement for the input

capacitor of a buck regulator is approximately 1/2 the DC load

current.

For a through hole design, several electrolytic capacitors may

be needed. For surface mount designs, solid tantalum

capacitors can be used, but caution must be exercised with

regard to the capacitor surge current rating. These capacitors

must be capable of handling the surge-current at power-up.

Some capacitor series available from reputable manufacturers

are surge current tested.

MOSFET Selection/Considerations

The ISL6431 requires two N-Channel power MOSFETs.

These should be selected based upon rDS(ON), gate supply

requirements, and thermal management requirements.

In high-current applications, the MOSFET power dissipation,

package selection and heatsink are the dominant design

factors. The power dissipation includes two loss components;

conduction loss and switching loss. The conduction losses

are the largest component of power dissipation for both the

upper and the lower MOSFETs. These losses are distributed

between the two MOSFETs according to duty factor (see the

equations below). Only the upper MOSFET has switching

losses, since the lower MOSFETs body diode or an external

Schottky rectifier across the lower MOSFET clamps the

switching node before the synchronous rectifier turns on.

These equations assume linear voltage-current transitions

and do not adequately model power loss due the reverse-

recovery of the lower MOSFET’s body diode. The gate-

charge losses are dissipated by the ISL6431 and don't heat

the MOSFETs. However, large gate-charge increases the

switching interval, tSW which increases the upper MOSFET

switching losses. Ensure that both MOSFETs are within their

maximum junction temperature at high ambient temperature

by calculating the temperature rise according to package

thermal-resistance specifications. A separate heatsink may

be necessary depending upon MOSFET power, package

type, ambient temperature and air flow.

PUPPER = Io2 x rDS(ON) x D +

1

2

Io x VIN x tSW x FS

PLOWER = Io2 x rDS(ON) x (1 - D)

Where: D is the duty cycle = VOUT / VIN,

tSW is the switching interval, and

FS is the switching frequency.

Given the reduced available gate bias voltage (5V),

logic-level or sub-logic-level transistors should be used for

both N-MOSFETs. Caution should be exercised with devices

exhibiting very low VGS(ON) characteristics. The shoot-

through protection present aboard the ISL6431 may be

circumvented by these MOSFETs if they have large parasitic

impedences and/or capacitances that would inhibit the gate

of the MOSFET from being discharged below its threshold

level before the complementary MOSFET is turned on.

+5V

DBOOT

VCC

ISL6431

+ VD -

+5V

BOOT

CBOOT

Q1

UGATE

PHASE

-

Q2

LGATE

+

GND

NOTE:

VG-S  VCC -VD

NOTE:

VG-S  VCC

FIGURE 7. UPPER GATE DRIVE BOOTSTRAP

Figure 7 shows the upper gate drive (BOOT pin) supplied by

a bootstrap circuit from VCC. The boot capacitor, CBOOT,

develops a floating supply voltage referenced to the PHASE

pin. The supply is refreshed to a voltage of VCC less the boot

diode drop (VD) each time the lower MOSFET, Q2, turns on.

FN9018 Rev 1.00

Jun 2002

Page 8 of 10

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