ISL88042IRTHFZ-T 데이터 시트보기 (PDF) - Renesas Electronics
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ISL88042IRTHFZ-T Datasheet PDF : 8 Pages
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ISL88042
point to some other voltage above 600mV according to
Equation 1:
VTRIP = 0.6V R1 + R2/R2
(EQ. 1)
Power-On Reset (POR)
Applying power to the ISL88042 activates a POR circuit, which
makes the reset pin(s) active (i.e. RST goes high while RST
goes low). These signals provide several benefits:
• They prevent the system microprocessor from starting to
operate with insufficient voltage.
• They prevent the processor from operating prior to
stabilization of the oscillator.
• They ensure that the monitored device is held out of
operation until internal registers are properly loaded.
• They allow time for an FPGA to download its configuration
prior to initialization of the circuit.
VTH1/VTH2
VDD /
V2MON 1V
The reset signal remains active until VDD rises above the
minimum voltage sense level for time period tPOR. This
ensures that the supply voltage has stabilized to sufficient
operating levels.
Manual Reset
The manual-reset input (MR) allows the user to trigger a reset
by using a push-button switch or by signaling the input low. The
MR input is an active low debounced input. Reset is asserted if
the MR pin is pulled low to less than 100mV for the minimum
MR pulse width or longer while the push-button is closed. After
MR is released, the reset output remains asserted low for tPOR
(200ms) and then is released.
Figures 2 and 3 illustrate the ISL88042’s operation.
>tMR
MR
RST
tPOR
tRPD
tPOR
tPOR
VXMON
RST
>tMD
FIGURE 2. POWER SUPPLY MONITORING DIAGRAM
VTH
tRPD
tPOR
FIGURE 3. VOLTAGE MONITORING DIAGRAM
FN6655 Rev 2.00
July 26, 2010
Page 5 of 8
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