74LV164D-Q100 데이터 시트보기 (PDF) - Nexperia B.V. All rights reserved
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74LV164D-Q100 Datasheet PDF : 19 Pages
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Nexperia
74LV164-Q100
8-bit serial-in/parallel-out shift register
6. Functional description
Table 3. Function table[1]
Operating mode Input
MR
CP
Reset (clear)
L
X
Shift
H
H
H
H
DSA
X
l
l
h
h
DSB
X
l
h
l
h
Output
Q0
L
L
L
L
H
Q1 to Q7
L to L
q0 to q6
q0 to q6
q0 to q6
q0 to q6
[1] H = HIGH voltage level;
L = LOW voltage level;
= LOW-to-HIGH clock transition;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;
q = lower case letter indicates the state of referenced input one set-up time prior to the LOW-to-HIGH CP transition.
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min Max Unit
VCC
IIK
IOK
IO
ICC
IGND
Tstg
Ptot
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
VI < 0.5 V or VI > VCC + 0.5 V
VO < 0.5 V or VO > VCC + 0.5 V
output source or sink current,
VO = 0.5 V to (VCC + 0.5 V)
Tamb = 40 C to +125 C
0.5 +7.0 V
-
20 mA
-
50 mA
[1] -
25 mA
-
-
65
[2] -
50 mA
50 mA
+150 C
500 mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] SO14 package: Ptot derates linearly with 8 mW/K above 70 C.
TSSOP14 package: Ptot derates linearly with 5.5 mW/K above 60 C.
DHVQFN14 package: Ptot derates linearly with 4.5 mW/K above 60 C.
74LV164_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 18 September 2014
© Nexperia B.V. 2017. All rights reserved
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