74LVT16373ADGG 데이터 시트보기 (PDF) - Nexperia B.V. All rights reserved
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74LVT16373ADGG Datasheet PDF : 14 Pages
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Nexperia
74LVT16373A
3.3 V 16-bit transparent D-type latch; 3-state
VI 90 %
tW
negative
pulse
VM
10 %
0V
tf
VI
positive
pulse
tr
90 %
VM
10 %
0V
tW
VM
tr
tf
VM
VI
G
VCC
VO
DUT
VEXT
RL
RT
CL
RL
Fig. 9.
001aae331
Test data is given in Table 9.
Definitions test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = Test voltage for switching times.
Test circuit for measuring switching times
Table 9. Test data
Input
VI
fi
2.7 V
≤ 10 MHz
tW
500 ns
tr, tf
≤ 2.5 ns
Load
CL
50 pF
RL
500 Ω
VEXT
tPHZ, tPZH
GND
tPLZ, tPZL
6V
tPLH, tPHL
open
74LVT16373A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 1 October 2018
© Nexperia B.V. 2018. All rights reserved
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