PCE84C882 데이터 시트보기 (PDF) - Philips Electronics

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PCE84C882

Microcontroller for monitor OSD and auto-sync applications

Philips Electronics 

Philips Semiconductors

Microcontroller for monitor OSD

and auto-sync applications

Preliminary specification

PCE84C882

6 RESET

The RESET pin may be used as an active LOW input to

initialize the microcontroller to a defined state.

An active reset can be generated by driving the RESET pin

from an external logic device. Such an active reset pulse

should not fall off before VDD has reached its

fxtal-dependent minimum operating voltage.

A Power-on-reset can be generated using an external RC

circuit. To avoid overload of the internal diode, an external

diode should be added in parallel if CRESET ≥ 2.2 µF. The

RC circuit is shown in Fig.3.

6.1 Reset trip level

The RESET trip voltage level for the PCE84C882 is in the

range 0.7 to 1.9 V.

If any input (for example Hsync) goes HIGH before VDD is

applied, latch-up may occur and in this situation the

PCE84C882 cannot be reset. The cause and effect of

latch-up is shown in Fig.4.

6.2 Reset status

• Derivative Registers reset status; see Table 38 for

details

• Program Counter 00H

• Memory Bank 0

• Register Bank 0

• Stack Pointer 00H

• All interrupts disabled

• Timer/event counter 1 stopped and cleared

• Timer pre-scaler modulo-32 (PS = 0)

• Timer flag cleared

• Serial I/O interface disabled (ESO = 0) and in slave

receiver mode

• Idle and Stop mode cleared.

handbook, halfpage

V DD

R RESET

( 100 kΩ)

RESET

C RESET

V SS

internal reset

PCA84C8XX

MLC259

Fig.3 External components for RESET pin.

handbook, halfpage

V DD

V DD

internal V DD

Hsync

R RESET

C RESET

V SS

HSYNCN

V SS

RESET

PCE84C882

internal reset

MGC710

Fig.4 The influence of an active HIGH signal being

applied before Power-on-reset.

1996 Jan 08

8

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