AD9954 데이터 시트보기 (PDF) - Analog Devices
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AD9954 Datasheet PDF : 40 Pages
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AD9954
Parameter
CMOS LOGIC INPUTS
Logic 1 Voltage @ DVDD_I/O (Pin 43) = 1.8 V
Logic 0 Voltage @ DVDD_I/O (Pin 43) = 1.8 V
Logic 1 Voltage @ DVDD_I/O (Pin 43) = 3.3 V
Logic 0 Voltage @ DVDD_I/O (Pin 43) = 3.3 V
Logic 1 Current
Logic 0 Current
Input Capacitance
CMOS LOGIC OUTPUTS (1 mA Load) DVDD_I/O = 1.8 V
Logic 1 Voltage
Logic 0 Voltage
CMOS LOGIC OUTPUTS (1 mA Load) DVDD_I/O = 3.3 V
Logic 1 Voltage
Logic 0 Voltage
POWER CONSUMPTION (AVDD = DVDD = 1.8 V)
Single-Tone Mode (Comparator Off )
With RAM or Linear Sweep Enabled
With Comparator Enabled
With RAM and Comparator Enabled
Rapid Power-Down Mode
Full-Sleep Mode
SYNCHRONIZATION FUNCTION4
Maximum Sync Clock Rate (DVDD_I/O = 1.8 V)
Maximum Sync Clock Rate (DVDD_I/O = 3.3 V)
SYNC_CLK Alignment Resolution5
Test
Temp Level Min
25°C I
1.25
25°C I
25°C I
2.2
25°C I
25°C V
25°C V
25°C V
25°C I
1.35
25°C I
25°C I
2.8
25°C I
25°C I
25°C I
25°C I
25°C I
25°C I
25°C I
25°C VI
62.5
25°C VI
100
25°C V
Typ Max
0.6
0.8
3
12
12
2
0.4
0.4
162 171
175 190
180 190
198 220
150 160
20 27
±1
Unit
V
V
V
V
μA
μA
pF
V
V
V
V
mW
mW
mW
mW
mW
mW
MHz
MHz
SYSCLK
cycles
1 Represents the cycle-to-cycle residual jitter from the comparator alone.
2 Wake-up time refers to the recovery from analog power-down modes (see section on Power-Down Modes of Operation). The primary limiting factor is the settling time of the PLL
multiplier in the reference circuitry. The wake-up time assumes there is no capacitor on DAC BP and that the recommended PLL loop filter values are used.
3 SYSCLK cycle refers to the clock frequency used on-chip to drive the DDS core. This is equal to the frequency of the reference source times the value of the PLL-based
reference clock multiplier.
4 SYNC_CLK = ¼ SYSCLK rate. Be sure the high speed sync enable bit, CFR2<11>, is programmed appropriately.
5 This parameter indicates that the digital synchronization feature cannot compensate for phase delays (timing skew) between system clock rising edges. If the system
clock edges are aligned, the synchronization function should not increase the skew between the two edges.
Rev. B | Page 6 of 40
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