AD9954 데이터 시트보기 (PDF) - Analog Devices
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AD9954 Datasheet PDF : 40 Pages
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Pin No.
31
35
36
37
Mnemonic
COMP_IN
PWRDWNCTL
RESET
IOSYNC
38
SDO
39
CS
40
SCLK
41
SDIO
43
DVDD_I/O
44
SYNC_IN
45
SYNC_CLK
46
OSK
47, 48
PS0, PS1
<49>
AGND
AD9954
I/O Description
I Comparator Complementary Input.
I Input Pin Used as an External Power-Down Control (see Table 9 for details).
I Active High Hardware Reset Pin. Assertion of the RESET pin forces the AD9954 to the default
state, as described in the right-hand column of Table 12, which is the I/O port register map.
I Asynchronous Active High Reset of the Serial Port Controller. When high, the current I/O
operation is immediately terminated, enabling a new I/O operation to commence once
IOSYNC is returned low. If unused, ground this pin; do not allow this pin to float.
O See Serial Interface Port Pin Description section for details.
I See Serial Interface Port Pin Description section for details.
I See Serial Interface Port Pin Description section for details.
I/O See Serial Interface Port Pin Description section for details.
I Digital Power Supply. This pin is for I/O cells only, 3.3 V.
I Input Signal Used to Synchronize Multiple AD9954s. This input is connected to the SYNC_CLK
output of a master AD9954.
O Clock Output Pin that Serves as a Synchronizer for External Hardware.
I Input Pin Used to Control the Direction of the Shaped On-Off Keying Function When Programmed
for Operation. OSK is synchronous to the SYNC_CLK pin. When OSK is disabled, this pin should
be tied to DGND.
I Input Pins Used to Select One of the Internal Phase/Frequency Profiles. PS1 and PS0 are
synchronous to the SYNC_CLK pin. Change on these pins triggers a transfer of the contents of
the chosen internal buffer memory to the I/O registers (sends an internal I/O UPDATE).
I The Exposed Paddle on the Bottom of the Package. It is a ground connection for the DAC and
must be attached to AGND in any board layout.
Rev. B | Page 9 of 40
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