ADM1064ACP 데이터 시트보기 (PDF) - Analog Devices

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ADM1064ACP

Super Sequencer™ with Voltage Readback ADC

Analog Devices 

ADM1064

Parameter

Input Reference Voltage on REFIN Pin,

VREFIN

Resolution

INL

Gain Error

Conversion Time

Offset Error

Input Noise

REFERENCE OUTPUT

Reference Output Voltage

Load Regulation

Minimum Load Capacitance

Load Regulation

PSRR

PROGRAMMABLE DRIVER OUTPUTS

High Voltage (Charge Pump) Mode

(PDO1–6)

Output Impedance

VOH

IOUTAVG

Standard (Digital Output) Mode (PDO1–10)

VOH

VOL

IOL2

ISINK 2

RPULL-UP

ISOURCE (VPn)2

Three-State Output Leakage Current

Oscillator Frequency

DIGITAL INPUTS (VXn, A0, A1)

Input High Voltage, VIH

Input Low Voltage, VIL

Input High Current, IIH

Input Low Current, IIL

Input Capacitance

Programmable Pull-Down Current,

IPULL-DOWN

SERIAL BUS DIGITAL INPUTS (SDA, SCL)

Input High Voltage, VIH

Input Low Voltage, VIL

Output Low Voltage, VOL2

Min

Typ

2.048

12

2.043

1

0.44

84

0.25

2.048

−0.25

0.25

2

60

500

11

12.5

10.5

12

20

2.4

VPU − 0.3

0

20

90

100

2.0

−1

5

20

2.0

Max

±2.5

±0.05

±2

2.053

14

13.5

4.5

0.50

20

60

2

10

110

0.8

1

0.8

0.4

Unit Test Conditions/Comments

V

Bits

LSB

%

ms

ms

LSB

LSBrms

Endpoint corrected, VREFIN = 2.048 V

VREFIN = 2.048 V

One conversion on one channel

All 12 channels selected, 16x averaging enabled

VREFIN = 2.048 V

Direct input (no attenuator)

V

No load

mV

Sourcing current, IDACnMAX = −100 µA

mV

Sinking current, IDACnMAX = 100 µA

µF

Capacitor required for decoupling, stability

mV Per 100 µA

dB

DC

kΩ

V

IOH = 0

V

IOH = 1µA

µA

2 V < VOH < 7 V

V

VPU (pull-up to VDDCAP or VPN) = 2.7 V, IOH = 0.5 mA

V

VPU to Vpn = 6.0 V, IOH = 0 mA

V

VPU ≤ 2.7 V, IOH = 0.5 mA

V

IOL = 20 mA

mA Maximum sink current per PDO pin

mA Maximum total sink for all PDOs

kΩ

Internal pull-up

mA Current load on any VPn pull-ups, that is, total

source current available through any number of

PDO pull-up switches configured onto any one

µA

VPDO = 14.4 V

kHz All on-chip time delays derived from this clock

V

Maximum VIN = 5.5 V

V

Maximum VIN = 5.5 V

µA

VIN = 5.5 V

µA

VIN = 0

pF

µA

VDDCAP = 4.75, TA = 25°C, if known logic state is

required

V

V

V

IOUT = −3.0 mA

Rev. 0 | Page 5 of 32

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