ADSP-21367BBP-2A 데이터 시트보기 (PDF) - Analog Devices

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ADSP-21367BBP-2A

SHARC Processors

Analog Devices 

ADSP-21367/ADSP-21368/ADSP-21369

Table 5. Pin List

Name

Type

State During/

After Reset

(ID = 00x)

Description

CLK_CFG1–0

I

Core/CLKIN Ratio Control. These pins set the start-up clock frequency. See

Table 8 for a description of the clock configuration modes.

Note that the operating frequency can be changed by programming the PLL

multiplier and divider in the PMCTL register at any time after the core comes out

of reset.

BOOT_CFG1–0

I

Boot Configuration Select. These pins select the boot mode for the processor.

The BOOT_CFG pins must be valid before reset is asserted. See Table 7 for a

description of the boot modes.

RESET

I

Processor Reset. Resets the processor to a known state. Upon deassertion, there

is a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins

program execution from the hardware reset vector address. The RESET input

must be asserted (low) at power-up.

XTAL

O

Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external

crystal.

CLKIN

I

Local Clock In. Used with XTAL. CLKIN is the processor’s clock input. It configures

the processors to use either its internal clock generator or an external clock

source. Connecting the necessary components to CLKIN and XTAL enables the

internal clock generator. Connecting the external clock to CLKIN while leaving

XTAL unconnected configures the processor to use an external clock such as an

external clock oscillator. CLKIN may not be halted, changed, or operated below

the specified frequency.

RESETOUT/

O/T

CLKOUT

Driven low/

driven high

Reset Out/Local Clock Out. Reset out provides a 4096 cycle delay that allows

the PLL to lock. This pin can also be configured as a CLKOUT signal to clock

synchronous peripherals and memory. The functionality can be switched

between the PLL output clock and reset out by setting Bit 12 of the PMCTL

register. The default is reset out.

BR4–1

I/O (pu)1

Pulled high/

pulled high

External Bus Request. Used by the ADSP-21368 processor to arbitrate for bus

mastership. A processor only drives its own BRx line (corresponding to the value

of its ID2-0 inputs) and monitors all others. In a system with less than four pro-

cessors, the unused BRx pins should be tied high; the processor’s own BRx line

must not be tied high or low because it is an output.

ID2–0

I (pd)

Processor ID. Determines which bus request (BR4–1) is used by the ADSP-21368

processor. ID = 001 corresponds to BR1, ID = 010 corresponds to BR2, and so on. Use

ID = 000 or 001 in single-processor systems. These lines are a system configura-

tion selection that should be hardwired or only changed at reset. ID = 101,110,

and 111 are reserved.

RPBA

I (pu)1

Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority

for the ADSP-21368 external bus arbitration is selected. When RPBA is low, fixed

priority is selected. This signal is a system configuration selection which must be

set to the same value on every processor in the system.

1 The pull-up is always enabled on the ADSP-21367 and ADSP-21369 processors. The pull-up on the ADSP-21368 processor is only enabled on the processor with ID2–0 = 00x

2 Pull-up can be enabled/disabled, value of pull-up cannot be programmed.

Rev. C | Page 14 of 56 | January 2008

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