ADSP-21367BBP-2A 데이터 시트보기 (PDF) - Analog Devices

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ADSP-21367BBP-2A

SHARC Processors

Analog Devices 

ADSP-21367/ADSP-21368/ADSP-21369

Table 12. Clock Periods

Timing

Requirements

Description1

tCK

CLKIN Clock Period

tCCLK

(Processor) Core Clock Period

tPCLK

(Peripheral) Clock Period = 2 × tCCLK

tSCLK

Serial Port Clock Period = (tCCLK) × SR

tSDCLK

SDRAM Clock Period = (tCCLK) × SDR

tSPICLK

SPI Clock Period = (tCCLK) × SPIR

1 where:

SR = serial port-to-core clock ratio (wide range, determined by SPORT CLKDIV

bits in DIVx register)

SPIR = SPI-to-core clock ratio (wide range, determined by SPIBAUD register

setting)

SPICLK = SPI clock

SDR = SDRAM-to-core clock ratio (values determined by Bits 20–18 of the

PMCTL register)

Figure 4 shows core to CLKIN relationships with external oscil-

lator or crystal. The shaded divider/multiplier blocks denote

where clock ratios can be set through hardware or software

using the power management control register (PMCTL). For

more information, see the ADSP-21368 SHARC Processor Hard-

ware Reference and Managing the Core PLL on Third-

Generation SHARC Processors (EE-290).

Use the exact timing information given. Do not attempt to

derive parameters from the addition or subtraction of others.

While addition or subtraction would yield meaningful results

for an individual device, the values given in this data sheet

reflect statistical variations and worst cases. Consequently, it is

not meaningful to add parameters to derive longer times. See

Figure 39 on Page 46 under Test Conditions for voltage refer-

ence levels.

Note that in the user application, the PLL multiplier value

should be selected in such a way that the VCO frequency (fVCO)

never exceeds 800 MHz.

2 × PLLM × fINPUT < 800

where:

fVCO is the VCO frequency.

PLLM is the multiplier value programmed.

fINPUT is the input frequency to the PLL in MHz.

fINPUT = CLKIN when the input divider is disabled and

fINPUT = CLKIN ÷ 2 when the input divider is enabled.

Switching Characteristics specify how the processor changes its

signals. Circuitry external to the processor must be designed for

compatibility with these signal characteristics. Switching char-

acteristics describe what the processor will do in a given

circumstance. Use switching characteristics to ensure that any

timing requirement of a device connected to the processor (such

as memory) is satisfied.

Timing Requirements apply to signals that are controlled by cir-

cuitry external to the processor, such as the data input for a read

operation. Timing requirements guarantee that the processor

operates correctly with other devices.

CLKIN

XTAL

BUF

PLLI

CLKIN CLK

DIVIDER

PMCTL

RESET

DELAY OF

4096 CLKIN

CYCLES

RESETOUT

PLL

LOOP

FILTER

VCO

PLL

MULTIPLIER

CLK_CFGx/PMCTL

CLKOUT

PLL

DIVIDER

PMCTL

CCLK SDRAM

DIVIDER

CLK_CFGx/

PMCTL

SDCLK

CLK_CFGx/

PMCTL

DIVIDE PCLK

BY 2

PMCTL

PCLK

CCLK

BUF

RESETOUT/

CLKOUT

CORERST

Figure 4. Core Clock and System Clock Relationship to CLKIN

Rev. C | Page 18 of 56 | January 2008

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