CY7C1046BN 데이터 시트보기 (PDF) - Cypress Semiconductor
부품명
상세내역
제조사
CY7C1046BN Datasheet PDF : 9 Pages
| |||
CY7C1046BN
Switching Characteristics (over the operating range)[4] (continued)
Parameter
WRITE CYCLE[8, 9]
Description
tWC
tSCE
tAW
tHA
tSA
tPWE
tSD
tHD
tLZWE
tHZWE
Write Cycle Time
CE LOW to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
WE HIGH to Low-Z[7]
WE LOW to High-Z[6, 7]
7C1046BN-15
Min
Max
Unit
15
ns
10
ns
10
ns
0
ns
0
ns
10
ns
8
ns
0
ns
3
ns
7
ns
Data Retention Characteristics (over the operating range)
Parameter
Description
Conditions[10]
VDR
ICCDR
tCDR[3]
tR
VCC for Data Retention
Data Retention Current
Com’l
Chip Deselect to Data Retention Time
Operation Recovery Time
VCC = VDR = 2.0V,
CE > VCC – 0.3V
VIN > VCC – 0.3V or VIN < 0.3V
Min Max Unit
2.0
V
200 μA
0
ns
200
μs
Data Retention Waveform
DATA RETENTION MODE
VCC
3.0V
VDR > 2V
3.0V
tCDR
tR
CE
1046B–5
Notes
8. The internal memory write time is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals
can terminate the write. The input data setup and hold timing must be referenced to the leading edge of the signal that terminates the write.
9. The minimum write cycle time for write cycle 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
10. No input may exceed VCC + 0.5V.
Document #: 001-11924 Rev. **
Page 4 of 9
[+] Feedback
Share Link: 