CY14B108N(2011) 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY14B108N Datasheet PDF : 25 Pages
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CY14B108L
CY14B108N
Table 1. Mode Selection
CE
WE
H
X
L
H
L
L
L
H
L
H
L
H
L
H
OE
BHE, BLE[5]
A15–A0[6]
Mode
I/O
Power
X
X
X
Not Selected Output High Z Standby
L
L
X
Read SRAM Output data
Active
X
L
X
Write SRAM Input data
Active
L
X
0x4E38
Read SRAM Output data
Active[7]
0xB1C7
Read SRAM Output data
0x83E0
Read SRAM Output data
0x7C1F
Read SRAM Output data
0x703F
Read SRAM Output data
0x8B45
AutoStore Output data
Disable
L
X
0x4E38
Read SRAM Output data
Active[7]
0xB1C7
Read SRAM Output data
0x83E0
Read SRAM Output data
0x7C1F
Read SRAM Output data
0x703F
Read SRAM Output data
0x4B46
AutoStore Output data
Enable
L
X
0x4E38
Read SRAM Output data Active ICC2[7]
0xB1C7
Read SRAM Output data
0x83E0
Read SRAM Output data
0x7C1F
Read SRAM Output data
0x703F
Read SRAM Output data
0x8FC0
Nonvolatile Output High Z
STORE
L
X
0x4E38
Read SRAM Output data
Active[7]
0xB1C7
Read SRAM Output data
0x83E0
Read SRAM Output data
0x7C1F
Read SRAM Output data
0x703F
Read SRAM Output data
0x4C63
Nonvolatile Output High Z
RECALL
Notes
5. BHE and BLE are applicable for × 16 configuration only.
6.
While there are 20 address lines on the CY14B108L
Rest of the address lines are don’t care.
(19
address
lines
on
the
CY14B108N),
only
the
13
address
lines
(A14–A2)
are
used
to
control
software
modes.
7. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
Document #: 001-45523 Rev. *J
Page 7 of 25
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