32174 데이터 시트보기 (PDF) - Renesas Electronics

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32174

32-bit RISC Single-chip Microcomputers

Renesas Electronics 

4.9.1 Reset Interrupt (RI) ................................................................................... 4-15

4.9.2 System Break Interrupt (SBI) .................................................................... 4-16

4.9.3 External Interrupt (EI) ............................................................................... 4-18

4.10 Trap Processing ............................................................................................ 4-20

4.10.1 Trap (TRAP) ........................................................................................... 4-20

4.11 EIT Priority Levels ......................................................................................... 4-22

4.12 Example of EIT Processing .......................................................................... 4-23

4.13 Precautions on EIT ....................................................................................... 4-25

CHAPTER 5 INTERRUPT CONTROLLER (ICU)

5.1 Outline of Interrupt Controller (ICU) ................................................................ 5-2

5.2 Interrupt Sources of Internal Peripheral I/Os ................................................. 5-4

5.3 ICU-Related Registers ...................................................................................... 5-6

5.3.1 Interrupt Vector Register ............................................................................. 5-7

5.3.2 Interrupt Mask Register .............................................................................. 5-8

5.3.3 SBI (System Break Interrupt) Control Register ........................................... 5-9

5.3.4 Interrupt Control Registers ........................................................................ 5-10

5.4 ICU Vector Table ............................................................................................. 5-14

5.5 Description of Interrupt Operation ................................................................ 5-17

5.5.1 Acceptance of Internal Peripheral I/O Interrupts ....................................... 5-17

5.5.2 Processing by Internal Peripheral I/O Interrupt by Handlers .................... 5-20

5.6 Description of System Break Interrupt (SBI) Operation .............................. 5-23

5.6.1 Acceptance of SBI .................................................................................... 5-23

5.6.2 SBI Processing by Handler ....................................................................... 5-23

CHAPTER 6 INTERNAL MEMORY

6.1 Outline of the Internal Memory ........................................................................ 6-2

6.2 Internal RAM ...................................................................................................... 6-2

6.3 Internal Flash Memory ...................................................................................... 6-3

6.4 Registers Associated with the Internal Flash Memory .................................. 6-4

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