ATMEGA48-15AZV 데이터 시트보기 (PDF) - Atmel Corporation
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ATMEGA48-15AZV Datasheet PDF : 340 Pages
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5.3.1
5.3.2
5.3.3
EEPROM Read/Write Access
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in Table 5-2. A self-timing function, however,
lets the user software detect when the next byte can be written. If the user code contains instruc-
tions that write the EEPROM, some precautions must be taken. In heavily filtered power
supplies, VCC is likely to rise or fall slowly on power-up/down. This causes the device for some
period of time to run at a voltage lower than specified as minimum for the clock frequency used.
See “Preventing EEPROM Corruption” on page 22 for details on how to avoid problems in these
situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
The EEPROM Address Register – EEARH and EEARL
Bit
Read/Write
Initial Value
15
–
EEAR7
7
R
R/W
0
X
14
–
EEAR6
6
R
R/W
0
X
13
–
EEAR5
5
R
R/W
0
X
12
–
EEAR4
4
R
R/W
0
X
11
–
EEAR3
3
R
R/W
0
X
10
–
EEAR2
2
R
R/W
0
X
9
–
EEAR1
1
R
R/W
0
X
8
EEAR8
EEAR0
0
R/W
R/W
X
X
EEARH
EEARL
• Bits 15..9 – Res: Reserved Bits
These bits are reserved bits in the ATmega48/88/168 and will always read as zero.
• Bits 8..0 – EEAR8..0: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the
256/512/512 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0
and 255/511/511. The initial value of EEAR is undefined. A proper value must be written before
the EEPROM may be accessed.
EEAR8 is an unused bit in ATmega48 and must always be written to zero.
The EEPROM Data Register – EEDR
Bit
Read/Write
Initial Value
7
6
5
4
3
2
1
0
MSB
LSB
EEDR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
• Bits 7..0 – EEDR7.0: EEPROM Data
For the EEPROM write operation, the EEDR Register contains the data to be written to the
EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the
EEDR contains the data read out from the EEPROM at the address given by EEAR.
18 Atmel ATmega48/88/168 Automotive
7530J–AVR–03/12
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