M5M5256DFP-85VLL-I 데이터 시트보기 (PDF) - MITSUBISHI ELECTRIC
부품명
상세내역
제조사
M5M5256DFP-85VLL-I Datasheet PDF : 7 Pages
| |||
'97.4.7
MITSUBISHI LSIs
M5M5256DFP,VP,RV -70VLL-I,-85VLL-I,
-70VXL-I,-85VXL-I
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS (Ta = -40~85°C, Vcc=3.3±0.3V, unless otherwise noted )
(1) MEASUREMENT CONDITIONS
Input pulse level···················VIH=2.2V,VIL=0.4V
Input rise and fall time··········5ns
Reference level····················VOH=VOL=1.5V
Output loads·························Fig.1,CL=30pF (-70VLL,-70VXL )
1TTL
DQ
CL=50pF (-85VLL,-85VXL )
CL=5pF (for ten,tdis)
Transition is measured ±500mV from steady
(Including
CL
scope and JIG)
state voltage. (for ten,tdis)
Fig.1 Output load
(2) READ CYCLE
Symbol
Parameter
tCR
ta(A)
ta(S)
ta(OE)
tdis(S)
tdis(OE)
ten(S)
ten(OE)
tV(A)
Read cycle time
Address access time
Chip select access time
Output enable access time
Output disable time after /S high
Output disable time after /OE high
Output enable time after /S low
Output enable time after /OE low
Data valid time after address
Limits
-70VLL, VXL -85VLL, VXL Unit
Min Max Min Max
70
85
ns
70
85 ns
70
85 ns
35
45 ns
25
25 ns
25
25 ns
5
10
ns
5
10
ns
10
10
ns
(3) WRITE CYCLE
Limits
Symbol
Parameter
-70VLL, VXL -85VLL, VXL Unit
Min Max Min Max
tCW
Write cycle time
70
85
ns
tw(W) Write pulse width
55
60
ns
tsu(A) Address setup time
0
0
ns
tsu(A-WH) Address setup time with respect to /W high 65
70
ns
tsu(S) Chip select setup time
65
70
ns
tsu(D) Data setup time
30
35
ns
th(D)
trec(W)
Data hold time
Write recovery time
0
0
ns
0
0
ns
tdis(W) Output disable time from /W low
25
25 ns
tdis(OE) Output disable time from /OE high
ten(W) Output enable time from /W high
25
25 ns
5
10
ns
ten(OE) Output enable time from /OE low
5
10
ns
MITSUBISHI
ELECTRIC
4
Share Link: 