MC12430FA 데이터 시트보기 (PDF) - Motorola => Freescale

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MC12430FA

High Frequency Clock Generator

Motorola => Freescale 

MC12430

VCC FOUT FOUT GND VCC TEST GND

25 24 23 22 21 20 19

S_CLOCK 26

18 N[1]

S_DATA 27

17 N[0]

S_LOAD 28

16 M[8]

PLL–VCC 1

28–Lead Pinout (Top View)

15 M[7]

FREF_EXT 2

14 M[6]

XTAL_SEL 3

13 M[5]

XTAL1 4

12 M[4]

56

7 8 9 10 11

XTAL2 OE P_LOAD M[0] M[1] M[2] M[3]

32–Lead Pinout

TBD

N[1:0]

00

01

10

11

Output Division

2

4

8

1

Input

XTAL_SEL

OE

0

FREF_EXT

Disabled

1

XTAL

Enabled

PIN DESCRIPTIONS

Pin Name

Function

Inputs

XTAL1, XTAL2

These pins form an oscillator when connected to an external series–resonant crystal.

S_LOAD

(Int. Pulldown)

This pin loads the configuration latches with the contents of the shift registers. The latches will be transparent when this

signal is HIGH, thus the data must be stable on the HIGH–to–LOW transition of S_LOAD for proper operation.

S_DATA

(Int. Pulldown)

This pin acts as the data input to the serial configuration shift registers.

S_CLOCK

(Int. Pulldown)

This pin serves to clock the serial configuration shift registers. Data from S_DATA is sampled on the rising edge.

P_LOAD

(Int. Pullup)

This pin loads the configuration latches with the contents of the parallel inputs .The latches will be transparent when this

signal is LOW, thus the parallel data must be stable on the LOW–to–HIGH transition of P_LOAD for proper operation.

M[8:0]

(Int. Pullup)

These pins are used to configure the PLL loop divider. They are sampled on the LOW–to–HIGH transition of P_LOAD. M[8]

is the MSB, M[0] is the LSB.

N[1:0]

(Int. Pullup)

These pins are used to configure the output divider modulus. They are sampled on the LOW–to–HIGH transition of

P_LOAD.

OE

(Int. Pullup)

Active HIGH Output Enable. The Enable is synchronous to eliminate possibility of runt pulse generation on the FOUT output.

Outputs

FOUT, FOUT

TEST

These differential positive–referenced ECL signals (PECL) are the output of the synthesizer.

The function of this output is determined by the serial configuration bits T[2:0]. The output is single–ended ECL.

Power

VCC

PLL_VCC

GND

This is the positive supply for the internal logic and the output buffer of the chip, and is connected to +3.3V or 5.0V

(VCC = PLL_VCC). Current drain through VCC ≈ 85mA.

This is the positive supply for the PLL, and should be as noise–free as possible for low–jitter operation. This supply is

connected to +3.3V or 5.0V (VCC = PLL_VCC). Current drain through PLL_VCC ≈ 15mA.

These pins are the negative supply for the chip and are normally all connected to ground.

Other

FREF_EXT

(Int. Pulldown)

LVCMOS/CMOS input which can be used as the PLL reference.

XTAL_SEL

(Int. Pullup)

LVCMOS/CMOS input that selects between the crystal and the FREF_EXT source for the PLL reference signal. A HIGH

selects the crystal input.

MOTOROLA

2

TIMING SOLUTIONS

BR1333 — Rev 6

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