APU429 데이터 시트보기 (PDF) - APLUS INTEGRATED CIRCUITS

부품명

상세내역

제조사

APU429

4-Bit Micro-controller With LCD Driver

APLUS INTEGRATED CIRCUITS 

4-Bit Micro-controller With LCD Driver

Features

y Low power and low voltage operation

y Powerful instruction set (150 instructions)

y Memory capacity

Ϋʳ Instruction ROM capacity 4096 x 16 bits

Ϋʳ Index ROM capacity 256 x 8 bits

Ϋʳ Internal RAM capacity 384 or 256 x 4 bits

y Input/Output ports of up to 20 pins

y 8-level subroutine nesting

y Built-in LCD driver, 8 x 42 = 336 segments

y Built-in EL driver, frequency or melody generator

y Built-in Resistance-to-Frequency Converter

y Built-in 2-channel 6/8-bit PWM output

y Built-in key strobe function

(Shared with segment pin)

y Built-in voltage doubler, halver, tripler

quadrupler charge pump circuit

y Two 6-bit programmable timers with

programmable clock source

y Watchdog timer

y 4 external & 3 internal interrupt resources

Ϋʳ External: INT, RFC, IOA/IOC/S port,

keystrobe

Ϋʳ Internal: TM1, TM2, Predivider

y Dual clock operation

y HALT and STOP function

General Description

The APU429 is an embedded high performance

4-bit micro-computer with an on-chip LCD driver. It

contains all the necessary functions in a single chip:

4-bit parallel processing ALU, ROM, RAM, I/O ports,

timer, clock generator, dual clock, RFC, EL-light,

LCD driver, look-up table, watchdog timer and

keyboard scanning. The instruction set includes not

only 4-bit operation and manipulation instructions

but also various conditional branch instructions and

LCD driver data transfer instructions which are

powerful and easy to use.

The HALT function stops any internal operations

other than the oscillator, divider and LCD driver in

order to minimize the power dissipation.

The STOP function stops all the clocks in the chip.

Block Diagram

S E G 35 38

S E G 31 34

S E G 39 42

S E G 27 30

COM 1 8

S E G 1 S E G 26 V D D 1 4

IO A P o rt

/R F C

IO B P o rt

/E L , B Z

IO C P o rt

/K E Y IN

IO D P o rt

/P W M

F re q u e n cy

G e n e ra to r

4 -B it D a ta B u s

T a b le R O M

256 x 8

In d e x S R A M

256 x 4

L C D D rive r

S egm entP LA

A LU

SRAM

128 x 4

CUP 1

CUP 2

CUP 3

P re -D ivid e r

W a tch d o g

T im e r

O scilla to r

Preliminary

2 x 6 B its

P re se t T im e r

C o n tro l

C ircu it

S1 S4

8 -L e ve ls S ta ck

1 2 -B it P ro g ra m

C o u n te r

In stru ctio n

D ecoder

M ask R O M

4096 x 16

1

Ver. 0.0

Share Link: