APU429 데이터 시트보기 (PDF) - APLUS INTEGRATED CIRCUITS
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APU429 Datasheet PDF : 18 Pages
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Pad No.
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
Pad Name
S4
VDD1
VDD2
VDD3
VDD4
CUP1
CUP2
CUP3
COM1
COM2
COM3
COM4
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11/KO1
SEG12/KO2
X
585.25
465.25
345.25
225.25
75.25
75.25
75.25
75.25
75.25
75.25
75.25
75.25
75.25
75.25
75.25
75.25
75.25
75.25
75.25
75.25
75.25
75.25
75.25
75.25
Y
2544.50
2544.50
2544.50
2544.50
2544.50
2394.50
2274.50
2154.50
2034.50
1914.50
1785.25
1665.25
1545.25
1425.25
1305.25
1185.25
1065.25
945.25
825.25
705.25
585.25
465.25
345.25
225.25
Pad No.
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
Pad Name
X
Y
SEG24/KO14
1425.25 75.25
SEG25/KO15
1545.25 75.25
SEG26/KO16
1665.25 75.25
SEG27/IOD1
1785.25 75.25
SEG28/IOD2
1971.50 75.25
SEH29/IOD3/PWM1 1971.50 225.25
SEH30/IOD4/PWM2 1971.50 345.25
SEG31/IOB1/ELC 1971.50 465.25
SEG32/IOB2/ELP 1971.50 585.25
SEG33/IOB3/BZB 1971.50 705.25
SEG34/IOB4/BZ 1971.50 825.25
SEG35/IOA1/CX 1971.50 945.25
SEG36/IOA2/RR 1971.50 1065.25
SEG37/IOA3/RT 1971.50 1185.25
SEG38/IOA4/RH 1971.50 1305.25
SEG39/IOC1/KI1 1971.50 1425.25
SEG40/IOC2/KI2 1971.50 1545.25
SEG41/IOC3/KI3 1971.50 1665.25
SEG42/IOC4/KI4 1971.50 1785.25
COM5
1971.50 1905.25
COM6
1971.50 2034.50
COM7
1971.50 2154.50
COM8
1971.50 2274.50
GND
1971.50 2394.50
Chip size : 2620 x 2050 Pm
Pad Descriptions
Pad Name
BAK
VDD1
VDD2
VDD3
VDD4
RESET
INT
TESTA
CUP1
CUP2
CUP3
I/O
Description
Positive back-up voltage.
In Li mode, connects a 0.1P capacitance to GND.
LCD drive voltage and positive supply voltage.
While in Ag mode, connects +1.5V to VDD1.
While in Li/ExtV mode, connects +3.0V to VDD2.
Input pin for LSI reset signal.
I With Internal pull-down resistor.
Input pin for external INT request signal.
I Falling edge or rising edge triggered by mask option.
Internal pull-down or pull-up resistor or floatting to be selected by mask option.
TESTA I Test signal input pin, internal pull-down resistor.
I Test signal input pin.
Switching pins for supplying the LCD driving voltage to the VDD1, 2, 3, 4 pins.
O Connects the CUP1, CUP2 and CUP3 pins with a nonpolarized electronic
capacitor if 1/2, 1/3 or 1/4 bias mode has been selected. In the STATIC mode,
these pins should be open.
Preliminary
3
Ver. 0.0
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