AT91M40800(2002) 데이터 시트보기 (PDF) - Atmel Corporation

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AT91M40800
(Rev.:2002)

AT91 ARM® Thumb® Microcontrollers

Atmel Corporation 

Product Overview

Power Supply

Input/Output

Considerations

Master Clock

Reset

NRST Pin

Watchdog Reset

Emulation Functions

Tri-state Mode

The AT91M40800 microcontroller has a unique type of power supply pin – VDD. The

VDD pin supplies the I/O pads and the device core. The supported voltage range on VDD

is 1.8V to 3.6V.

The AT91M40800 microcontroller I/O pads are 5V-tolerant, enabling them to interface

with external 5V devices without any additional components. Thus, the devices accept

5V (3V) on the inputs even if powered at 3V (2V). For further information, refer to the

“AT91M40800 Electrical Characteristics” datasheet.

After the reset, the peripheral I/Os are initialized as inputs to provide the user with maxi-

mum flexibility. It is recommended that in any application phase, the inputs to the

AT91M40800 microcontroller be held at valid logic levels to minimize the power

consumption.

The AT91M40800 microcontroller has a fully static design and works on the Master

Clock (MCK), provided on the MCKI pin from an external source.

The Master Clock is also provided as an output of the device on the pin MCKO, which is

multiplexed with a general-purpose I/O line. While NRST is active, MCKO remains low.

After the reset, the MCKO is valid and outputs an image of the MCK signal. The PIO

controller must be programmed to use this pin as standard I/O line.

Reset restores the default states of the user interface registers (defined in the user inter-

face of each peripheral), and forces the ARM7TDMI to perform the next instruction fetch

from address zero. Except for the program counter the ARM7TDMI registers do not

have defined reset states.

NRST is active low-level input. It is asserted asynchronously, but exit from reset is syn-

chronized internally to the MCK. The signal presented on MCKI must be active within

the specification for a minimum of 10 clock cycles up to the rising edge of NRST, to

ensure correct operation.

The first processor fetch occurs 80 clock cycles after the rising edge of NRST.

The watchdog can be programmed to generate an internal reset. In this case, the reset

has the same effect as the NRST pin assertion, but the pins BMS and NTRI are not

sampled. Boot Mode and Tri-state Mode are not updated. If the NRST pin is asserted

and the watchdog triggers the internal reset, the NRST pin has priority.

The AT91M40800 microcontroller provides a Tri-state mode, which is used for debug

purposes. This enables the connection of an emulator probe to an application board

without having to desolder the device from the target board. In Tri-state mode, all the

output pin drivers of the AT91M40800 microcontroller is disabled.

To enter Tri-state mode, the pin NTRI must be held low during the last 10 clock cycles

before the rising edge of NRST. For normal operation the pin NTRI must be held high

during reset by a resistor of up to 400K Ohm.

NTRI is multiplexed with I/O line P21 and USART1 serial data transmit line TXD1.

8 AT91M40800

1348DS–ATARM–02/02

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