BUK102-50GL 데이터 시트보기 (PDF) - Philips Electronics
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BUK102-50GL Datasheet PDF : 11 Pages
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Philips Semiconductors
PowerMOS transistor
Logic level TOPFET
Product specification
BUK102-50GL
VDD
RL
D
TOPFET
I
P
D.U.T.
RI
VIS
S
ID measure
0V
0R1
Fig.20. Test circuit for resistive load switching times.
VDD = VCL
LD
t p : adjust for correct ID
D
TOPFET
I
P
D.U.T.
RI
VIS
S
ID measure
0V
0R1
Fig.23. Test circuit for inductive load switching times.
RESISTIVE TURN-ON
15
VDS / V
10
90%
td on
tr
5
BUK102-50GL
ID / A
VIS / V
10%
10%
0
0
10
20
Time / us
Fig.21. Typical switching waveforms, resistive load.
VDD = 13 V; RL = 1.1 Ω; RI = 50 Ω, Tj = 25 ˚C.
RESISTIVE TURN-OFF
15
ID / A
10
90%
BUK102-50GL
VDS / V
td off
tf
VIS / V
5
90%
10%
0
0
10
20
Time / us
Fig.22. Typical switching waveforms, resistive load.
VDD = 13 V; RL = 1.1 Ω; RI = 50 Ω, Tj = 25 ˚C.
INDUCTIVE TURN-ON
10 VDS / V
90%
td on
tr
5
BUK102-50GL
ID / A
VIS / V
10%
10%
0
0
10
20
Time / us
Fig.24. Typical switching waveforms, inductive load.
VDD = 13 V; ID = 11 A; RI = 50 Ω, Tj = 25 ˚C.
INDUCTIVE TURN-OFF
ID / A
10
BUK102-50GL
90%
VDS / V
td off
tf
5
90%
VIS / V
10%
0
-1
0
10
20
Time / us
Fig.25. Typical switching waveforms, inductive load.
VDD = 13 V; ID = 11 A; RI = 50 Ω, Tj = 25 ˚C.
January 1993
8
Rev 1.200
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