BUK102-50GL 데이터 시트보기 (PDF) - Philips Electronics
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BUK102-50GL Datasheet PDF : 11 Pages
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Philips Semiconductors
PowerMOS transistor
Logic level TOPFET
Product specification
BUK102-50GL
EDSM%
120
110
100
90
80
70
60
50
40
30
20
10
0
0
20
40
60
80 100 120 140
Tmb / C
Fig.26. Normalised limiting clamping energy.
EDSM% = f(Tmb); conditions: ID = 25 A; VIS = 10 V
VDS
0
ID
0
VIS
0
V(CL)DSS
VDD
L
+ VDD
VDS
D
TOPFET
I
P
D.U.T.
-
-ID/100
RIS
Schottky
S
R 01
shunt
Fig.27. Clamping energy test circuit, RIS = 50 Ω.
EDSM = 0.5 ⋅ L ID2 ⋅ V(CL)DSS/(V(CL)DSS − VDD)
Idss
1 mA
100 uA
10 uA
typ.
1 uA
100 nA
0
20
40
60
80 100 120 140
Tj / C
Fig.28. Typical off-state leakage current.
IDSS = f(Tj); Conditions: VDS = 40 V; IIS = 0 V.
Iiso normalised to 25 C
1.5
1
0.5
-60
-20
20
60
100
140
180
Tj / C
Fig.29. Normalised input current (normal operation).
IIS/IIS25 ˚C = f(Tj); VIS = 5 V
Iisl normalised to 25 C
1.5
1
0.5
-60
-20
20
60
100
140
180
Tj / C
Fig.30. Normalised input current (protection latched).
IISL/IISL25 ˚C = f(Tj); VIS = 5 V
January 1993
9
Rev 1.200
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