Philips Semiconductors
BUK95/9629-100B
TrenchMOS™ logic level FET
120
Pder
(%)
80
03na19
60
ID
(A)
40
03nm56
40
20
0
0
50
100
150
200
Tmb (°C)
Pder = P-------P----t--o---t------- × 100%
t o t ( 25 °C )
Fig 1. Normalized total power dissipation as a
function of mounting base temperature.
0
0
50
VGS ≥ 5 V
100
150
200
Tmb (°C)
Fig 2. Continuous drain current as a function of
mounting base temperature.
103
03nm54
ID
(A)
102
Limit RDSon = VDS / ID
tp = 10 µ s
100 µ s
10
DC
1 ms
10 ms
100 ms
1
1
10
102
103
VDS (V)
Tmb = 25 °C; IDM single pulse.
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 11249
Product data
Rev. 01 — 18 April 2003
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
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