IDT71V3558SA100BQG 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT71V3558SA100BQG

128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs

Integrated Device Technology 

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

Recommended Operating

Temperature and Supply Voltage

Grade

Temperature(1)

VSS

VDD

VDDQ

Commercial

0°C to +70°C

0V 3.3V± 5% 3.3V± 5%

Industrial

-40°C to +85°C 0V 3.3V± 5% 3.3V± 5%

NOTES:

1. TA is the "instant on" case temperature.

5281 tbl 05

Pin Configuration - 128K x 36

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

I/OP3

I/O16

I/O17

VDDQ

VSS

I/O18

I/O19

I/O20

I/O21

VSS

VDDQ

I/O22

I/O23

VDD(1)

VDD

VDD(1)

VSS

I/O24

I/O25

VDDQ

VSS

I/O26

I/O27

I/O28

I/O29

VSS

VDDQ

I/O30

I/O31

I/OP4

1

80

2

79

3

78

4

77

5

76

6

75

7

74

8

73

9

72

10

71

11

70

12

69

13

68

14

67

15

66

16

65

17

64

18

63

19

62

20

61

21

60

22

59

23

58

24

57

25

56

26

55

27

54

28

53

29

52

30

51

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

I/OP2

I/O15

I/O14

VDDQ

VSS

I/O13

I/O12

I/O11

I/O10

VSS

VDDQ

I/O9

I/O8

VSS

VDD(1)

VDD

VSS/ZZ(3)

I/O7

I/O6

VDDQ

VSS

I/O5

I/O4

I/O3

I/O2

, VSS

VDDQ

I/O1

I/O0

I/OP1

5281 drw 02

Top View

100 TQFP

NOTES:

1. Pins 14, 16 and 66 do not have to be connected directly to VDD as long as the input voltage is ≥ VIH.

2. Pins 83 and 84 are reserved for future 8M and 16M respectively.

3. Pin 64 does not have to be connected directly to VSS as long as the input voltage is ≤ VIL; on the latest die revision this

pin supports ZZ (sleep mode).

6.452

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