RMWL26001 데이터 시트보기 (PDF) - Fairchild Semiconductor
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RMWL26001 Datasheet PDF : 8 Pages
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Electrical Characteristics (At 25°C), 50 Ω system, Vd = +4V, Quiescent current (Idg) = 65 mA
Parameter
Frequency Range
Gate Supply Voltage1 (Vg)
Gain at Pin = -15dBm (21–24GHz)
Gain at Pin = -15dBm (21–26.5GHz)
GainVariation vs Freq. (21–26.5GHz)
Gain at 1 dBm Compression (21–26.5GHz)
Power Output at 1dB Compression
Drain Current at Pin = -15dBm
Drain Current at 1dB Compression
Input Return Loss (Pin = -15dBm)
Output Return Loss (Pin = -15dBm)
Noise Figure
OIP3
Min
Typ
Max
21
26.5
0.5
20
22
26
20
21
26
2.8
20
10
65
80
12
12
2.9
4.0
22
Units
GHz
V
dB
dB
dB
dB
dBm
mA
mA
dB
dB
dB
dBm
Note:
1: Typical range of negative gate voltage is -0.8 to -0.2 V to set typical Idq of 65 mA
Application Information
CAUTION: THIS IS AN ESD SENSITIVE DEVICE.
Chip carrier material should be selected to have GaAs compatible thermal coefficient of expansion and high thermal
conductivity such as copper molybdenum or copper tungsten. The chip carrier should be machined, finished flat, plated with
gold over nickel and should be capable of withstanding 325°C for 15 minutes.
Die attachment should utilize Gold/Tin (80/20) eutectic alloy solder and should avoid hydrogen environment for PHEMT
devices. Note that the backside of the chip is gold plated and is used as RF and DC ground.
These GaAs devices should be handled with care and stored in dry nitrogen environment to prevent contamination of
bonding surfaces. These are ESD sensitive devices and should be handled with appropriate precaution including the use of
wrist grounding straps. All die attach and wire/ribbon bond equipment must be well grounded to prevent static discharges
through the device.
Recommended wire bonding uses 3 mils wide and 0.5 mil thick gold ribbon with lengths as short as practical allowing for
appropriate stress relief. The RF input and output bonds should be typically 0.012" long corresponding to a typical 2 mil gap
between the chip and the substrate material.
DRAIN DRAIN DRAIN DRAIN
SUPPLY SUPPLY SUPPLY SUPPLY
Vd1
Vd2
Vd3
Vd4
RF IN
MMIC CHIP
RF OUT
GROUND
(Back of the Chip)
GATE SUPPLY
Vg
Figure 1. Functional Block Diagram
©2004 Fairchild Semiconductor Corporation
RMWL26001 Rev. D
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