ST18D952 데이터 시트보기 (PDF) - STMicroelectronics

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ST18D952

DIGITAL SIGNAL PROCESSOR (DSP) CHIP

STMicroelectronics 

ST18952

Table 2.4 General purpose parallel port / Interrupt requests (8 pins)

Pin name

P_ITRQ0-7

Type Description

I/O Multiplexed input/output. Parallel port I/O or external interrupt request (ITRQ).

Table 2.5 Clocks (6 pins)

Pin name

EXTAL

XTAL

MCLK

CLK_MODE

INCYCLE

CLKOUT

Type

I

O

I

I

O

O

Description

Oscillator input.

Oscillator output. Nominal oscillator frequency is 27 MHz.

Master clock input (use of external clock generator).

Clock mode select input.

When low the oscillator and internal PLL are enabled. The 950 receives its

Master clock from the PLL at 5 times the oscillator frequency.

When high the PLL is disabled. The D950 receives its master clock from

MCLK.

Instruction cycle.

Asserted high for 1 CLKOUT cycle at the beginning of instruction cycle.

Output clock (at input clock/2 frequency).

Table 2.6 Bus control (3 pins)

Pin name

DTACK

HOLD

HOLDACK

Type

I

I

O

Description

Data transfer acknowledge input. Active low.

It is combined in a OR gate with BSU DTACK output in order to generate the

DTACK signal for the D950Core. It controls extension of bus cycles by inser-

tion of wait-states when using external memory either through Bus-switch or

direct extension.

External Bus Hold request input. Active low.

Hold acknowledge output. Active low.

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