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LH28F008SC

8M (1M × 8) Flash Memory

Sharp Electronics 

LH28F008SC

8M (1M × 8) Flash Memory

PIN DESCRIPTION

SYMBOL

TYPE

NAME AND FUNCTION

A0 - A19

DQ0 - DQ7

CE »

RP »

OE »

INPUT

INPUT/OUTPUT

INPUT

INPUT

INPUT

ADDRESS INPUTS: Inputs for addresses during read and write operations.

Addresses are internally latched during a write cycle.

DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles; outputs

data during memory array, status register and identifier code read cycles. Data pins

float to high-impedance when the chip is deselected or outputs are disabled. Data is

internally latched during a write cycle.

CHIP ENABLE: Activates the device’s control logic input buffers, decoders, and

sense amplifiers. CE » high deselects the device and reduces power consumption to

standby levels.

RESET/DEEP POWER-DOWN: Puts the device in deep power-down mode and resets

internal automation. RP» high enables normal operation. When driven low, RP» inhibits

write operations which provides data protection during power transitions. Exit from deep

power-down sets the device to read array mode. RP» at VHH enables setting of the

master lock-bit and enables configuration of block lock-bits when the master lock-bit is

set. RP » = VHH overrides block lock-bits thereby enabling block erase and byte write

operation to locked memeory blocks. Block erase, byte write, or lock-bit configuration

with VIH < RP » < VHH produce spurious results and should not be attempted.

OUTPUT ENABLE: Gates the device’s outputs during a read cycle.

WE

INPUT

RY»/BY » OUTPUT

WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are

latched on the rising edge of the WE Pulse.

READY/BUSY: Indicates the status of the internal WSM. When low, the WSM is

performing an internal operation (block erase, byte write, or lock-bit configuration).

RY »/BY » high indicates that the WSM is ready for new commands, block erase is

suspended, and byte write is inactive, byte write is suspended, or the device is in

deep power-down mode. RY»/BY » is always active and does not float when the chip

is deselected or data outputs are disabled.

VPP

SUPPLY

VCC

SUPPLY

BLOCK ERASE/BYTE WRITE, LOCK-BIT CONFIGURATION POWER SUPPLY:

For erasing array blocks, writing bytes, or configuring lock-bits. With VPP ≤ VLKO,

memory contents cannot be altered. Block erase, byte write, and lock-bit configura-

tion with an invalid VPP (see DC Characteristics) produce spurious results and

should not be attempted.

DEVICE POWER SUPPLY: Internal detection configures the device for 3.3 V or 5 V

operation. To switch from one voltage to another, ramp VCC down to GND and then

ramp VCC to the new voltage. Do not float any power pins. With VCC ≤ VLKO, all write

attempts to the flash memory are inhibited. Device operations at invalid VCC voltage

(see DC Characteristics) produce spurious results and should not be attempted.

GND SUPPLY

GROUND: Do not float any pins

NC

NO CONNECT: Lead is not internal connected; it may be driven or floated.

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