MU9C3480L-12DC 데이터 시트보기 (PDF) - Music Semiconductors

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MU9C3480L-12DC

LANCAM®

Music Semiconductors 

MU9C3480L

LANCAM®

PIN DESCRIPTIONS (CONT’D)

/W (Write Enable, Input, TTL)

/MA (Device Match Flag, Output, TTL)

The /W input selects the direction of data flow during a

device cycle. /W LOW selects a Write cycle, and /W

HIGH selects a Read cycle.

/CM (Data/Command Select, Input, TTL)

The /CM input selects whether the input signals on

DQ15-DQ0 are data or commands. /CM LOW selects

Command cycles, and /CM HIGH selects Data cycles.

/EC (Enable Daisy Chain, Input, TTL)

The /EC signal performs two functions. The /EC input

enables the /MF output to show the results of a

comparison. If /EC is LOW at the falling edge of /E in

a given cycle, the /MF output is enabled. Otherwise, the

/MF output is held HIGH. The /EC signal also enables

the /MF-/MI daisy-chain, which serves to select the

device with the highest-priority match in a string of

LANCAMs. Tables 8a and 8b explain the effect of the

/EC signal on a device with and without a match in both

the 1480 and 2480 modes. /EC must be HIGH during

initialization.

/MF (Match Flag, Output, TTL)

The /MF output goes LOW when one or more valid

matches occur during a compare cycle. /MF becomes

valid after /E goes HIGH on the cycle that enables the

daisy chain (the first cycle that /EC is registered LOW

by the previous falling edge of /E; see Figure 6). In a

daisy-chain, valid match(es) in higher priority devices

are passed from the /MI input to /MF. If the daisy chain

is enabled but the match flag is disabled in the control

register, the /MF output only depends on the /MI input

of the device (/MF=/MI). /MF is HIGH if there is no

match or when the daisy chain is disabled (/E goes

HIGH when /EC was HIGH on the previous falling edge

of /E). The System Match flag is the /MF pin of the last

device in the daisy-chain. /MF will be reset when the

active configuration register set is changed.

The /MA output is LOW when one or more valid

matches occur during the current or the last previous

compare cycle. The /MA output is not qualified by /EC

or /MI, and reflects the match flag from that specific

device’s Status register. /MA will be reset when the

active register set is changed.

/MM (Device Multiple Match Flag, Output, TTL)

The /MM output is LOW when more than one valid

match occurs during the current or the last previous

compare cycle. The /MM output is not qualified by /EC

or /MI, and reflects the multiple match flag from that

specific device’s Status register. /MM will be reset when

the active register set is changed.

/FF (Full Flag, Output, TTL)

If enabled in the control register, the /FF output goes

LOW when no empty memory locations exist within the

device (and in the daisy-chain above the device as

indicated by the /FI pin). The System Full flag is the /FF

pin of the last device in the daisy chain, and the Next

Free address resides in the device with /FI LOW and

/FF HIGH. If disabled in the control register, the /FF

output only depends on the /FI input (/FF = /FI).

/FI (Full Input, Input, TTL)

The /FI input generates a CAM-Memory-System-Full

indication in vertically cascaded systems. It is

connected to the /FF output of the previous (next-higher

priority) device in the daisy chain. The /FI pin on the

highest priority device must be tied LOW.

/RESET (Reset, Input, TTL)

Driving the /RESET pin LOW resets the device to the

conditions shown in Table 5. The /RESET pin should

be driven by TTL levels, not directly by an RC timeout.

/E must be kept HIGH during /RESET.

/MI (Match Input, Input, TTL)

The /MI input prioritizes devices in vertically cascaded

systems. It is connected to the /MF output of the

previous (next higher-priority) device in the daisy chain.

The /MI pin on the highest priority device must be tied

HIGH.

/W

LOW

LOW

HIGH

HIGH

/CM

LOW

HIGH

LOW

HIGH

Cycle Type

Command Write Cycle

Data Write Cycle

Command Read Cycle

Data Read Cycle

VCC, GND (Positive Power Supply, Ground)

These pins are the power supply connections to the

MU9C3480L. VCC must meet the 3.3 + 0.3 volt

requirements in the Operating Conditions section

relative to the GND pins, which are at 0 Volts (system

reference potential), for correct operation of the device.

All the ground and power pins must be connected to

their respective planes with adequate bulk and high

frequency bypassing capacitors in close proximity to

the device.

Table 2: I/O Cycles

Rev. 1.0 Draft Web

3

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