MU9C3480L-12DC 데이터 시트보기 (PDF) - Music Semiconductors
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MU9C3480L-12DC Datasheet PDF : 24 Pages
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MU9C3480L
LANCAM®
OPERATIONAL CHARACTERISTICS (CONT’D)
CycleType /E /CM /W I/O SPS SPD TCO Operation
Status
Notes
Com Write L L L
IN
Load Instruction decoder
1
IN
√ Load Address register
2, 3
IN
√ Load Control register
3
IN
√ Load Page Address register
3
IN
√ Load Segment Control register
3
IN
√ Load Device Select register
3
IN
Deselected
10
Com Read L L H OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
HIGH-Z
√ Read Next Free Address register
3
√ Read Address register
3
Read Status Register bits 15-0
4
Read Status Register bits 31-16
5
√ Read Control Register
3
√ Read Page Address Register
3
√ Read Segment Control Register
3
√ Read Device Select Register
3
√ Read Current Persistent Source or Destination 3,11
Deselected
10
Data Write L H L
IN
IN
IN
IN
IN
IN
IN
√
Load Comparand Register
6, 9
√
Load Mask Register 1
7, 9
√
Load Mask Register 2
7, 9
√
Write Memory Array at Address
7,9
√
Write Memory Array at Next Free Address
7, 9
√
Write Memory Array at Highest-priority Match 7, 9
Deselected
10
Data Read L H H OUT √
OUT √
OUT √
OUT √
OUT √
HIGH-Z
H X X HIGH-Z
Read Comparand Register
6, 9
Read Mask Register 1
8,9
Read Mask Register 2
8,9
Read Memory Array at Address
8,9
Read Memory Array at Highest-priority Match 8,9
Deselected
10
Deselected
Notes
1. Default Command Write cycle destination (does not require a TCO instruction).
2. Default Command Write Cycle destination (no TCO instruction required) if Address flag was set in bit IR11 of the
instruction loaded in the previous cycle.
3. Loaded or read on the consecutive Command Write or Read cycle after a TCO instruction has been loaded. Active
for one Command Write or Read cycle only. NFA register cannot be loaded this way.
4. Default Command Read cycle source (does not require a TCO instruction).
5. Default Command read cycle source (no //tco instruction required) if the previous cycle was a Command /read of
status register bits 15-0. If next cycle is not a Command Read cycle, any subsequent Command Read cycle will access
the Status register bits 15-0.
6. Default persistent source and destination on power-up and after Reset. If other resources were sources or
destinations, SPD CR or SPS CR restores the Comparand register as the destination or source.
7. Selected by executing a Select Persistent Destination Instruction.
8. Selected by executing a Select Persistent Source Instruction.
9. Access may require multiple 16-bit Read or Write cycles. The Segment Control register is used to control the
selection of the desired 16-bit segment(s) by establishing the Segment counters’ limits and start values.
10. Device is deselected if Device Select register setting does not equal Page Address register setting, unless the Device
Select register is set to FFFFH which allows only write access to the device. (Writes to the Device Select register are
always active.) Device may also be deselected under locked daisy-chain conditions as shown in Tables 8a and 8b.
11. A Command Read cycle after a TCO PS or TCO PD read back the Instruction decoder bits that were last set to
select a persistant source or destination.
Table 3: Input/Output Operations
Rev. 1.0 Draft Web
7
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