72SD3232BRPFK 데이터 시트보기 (PDF) - MAXWELL TECHNOLOGIES
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72SD3232BRPFK Datasheet PDF : 41 Pages
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1 Gbit(8-Meg X 32-Bit X 4-Banks) SDRAM
Pin Functions:
72SD3232B
CLK (INPUT PIN): CLK are the master clock inputs to this pin. The other input signals are referred at CLK rising
edge.
CS (INPUT PIN): When CS is Low, the command input cycle becomes valid. When CS is High, all inputs are
ignored. However, internal operations (bank active, burst operations, etc.) are held.
RAS, CAS AND WE (INPUT PINS): Although these pin names are the same as those of conventional DRAMs,
they function in a different way. These pins define operation commands (read, write, etc.) depending on the
combination of their voltage levels. For details, refer to the command operations section.
A0 TO A12 (INPUT PINS): Row address (AX0 to AX12) is determined by A0 to A12 level at the bank active
command cycle CLK rising edge. Column address (AY0 to AY9) is determined by A0 to A9 level at the read
or write command cycle CLK rising edge. And this column address becomes burst access start address.
A10 defines the precharge mode. When A10 = High at the precharge command cycle, all banks are pre-
charged. But when A10 = Low at the precharge command cycle, only the bank that is selected by BA0/BA1
(BS) is pre charged. For details refer to the command operation section.
BA0/BA1 (INPUT PINS): BA0/BA1 are bank select signals (BS). The memory array of the 72SD3232B is
divided into bank 0, bank 1, bank 2 and bank 3. The 72SD3232B contains 8192-row X 1024-column X 32-
bit. If BA0 and BA1 is Low, bank 0 is selected. If BA0 is Low and BA1 is High, bank 1 is selected. If BA0 is
High and BA1 is Low, bank 2 is selected. If BAO is High and BA1 is High, bank 3 is selected.
CKE (INPUT PIN): This pin determines whether or not the next CLK is valid. If CKE is High, the next CLK rising
edge is valid. If CKE is Low, the next CLK rising edge is invalid. This pin is used for power-down mode,
clock suspend mode and self refresh mode1.
DQM1 - DQM4 (INPUT PIN): DQM1 - DQM4 control input/output buffers
Read operation: If DQM1 - DQM4 are High, the output buffers becomes High-Z. If the DQM1- DQM4 are
Low, the output buffers becomes Low-Z. (The latency of DQM1 - DQM4 during reading is 2 clock cycles.)
Write operation: If DQM1 - DQM4 are High, the previous data is held ( the new data is not written). If the
DQM1 - DQM4 are Low, the data is written. ( The latency of DQM1 - DQM4 during writing is 0 clock cycles.)
DQ0 TO DQ31 (DQ PINS): Data is input to and output from these pins ( DQ0 to DQ31).
VCC AND VCCQ (POWER SUPPLY PINS): 3.3V is applied. ( VCC is for the internal circuit and VCCQ is for the output
buffer.)
VSS AND VSSQ (POWER SUPPLY PINS): Ground is connected. (VSS is for the internal circuit and VSSQ is for the
output buffer.)
1. Use self refresh at temperatures below 70°C only.
06.11.08 Rev 1
All data sheets are subject to change without notice 7
©2008 Maxwell Technologies
All rights reserved.
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