M95320-DRE 데이터 시트보기 (PDF) - STMicroelectronics

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M95320-DRE

32-Kbit serial SPI bus EEPROM - 105 °C Operation

STMicroelectronics 

Signal description

2

Signal description

M95320-DRE

All input signals must be held high or low (according to voltages of VIH or VIL, as specified in

Table 12). These signals are described below.

2.1

Serial Data output (Q)

This output signal is used to transfer data serially out of the device during a Read operation.

Data is shifted out on the falling edge of Serial Clock (C), most significant bit (MSB) first. In

all other cases, the Serial Data output is in high impedance.

2.2

Serial Data input (D)

This input signal is used to transfer data serially into the device. D input receives

instructions, addresses, and the data to be written. Values are latched on the rising edge of

Serial Clock (C), most significant bit (MSB) first.

2.3

Serial Clock (C)

This input signal allows to synchronize the timing of the serial interface. Instructions,

addresses, or data present at Serial Data Input (D) are latched on the rising edge of Serial

Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C).

2.4

Chip Select (S)

Driving Chip Select (S) low selects the device in order to start communication. Driving Chip

Select (S) high deselects the device and Serial Data output (Q) enters the high impedance

state.

2.5

Hold (HOLD)

The Hold (HOLD) signal is used to pause any serial communications with the device without

deselecting the device.

2.6

Write Protect (W)

This pin is used to write-protect the Status Register.

2.7

VSS ground

VSS is the reference for all signals, including the VCC supply voltage.

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DocID027471 Rev 2

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