ADSP-BF539(RevA) 데이터 시트보기 (PDF) - Analog Devices
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ADSP-BF539 Datasheet PDF : 60 Pages
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filtered by the PPI. After synchronizing to the start of Field 1,
the PPI will ignore incoming samples until it sees an SAV code.
The user specifies the number of active video lines per frame (in
PPI_COUNT register).
Vertical Blanking Interval Mode
In this mode, the PPI only transfers vertical blanking interval
(VBI) data.
Entire Field Mode
In this mode, the entire incoming bit stream is read in through
the PPI. This includes active video, control preamble sequences,
and ancillary data that can be embedded in horizontal and verti-
cal blanking intervals. Data transfer starts immediately after
synchronization to Field 1.
CONTROLLER AREA NETWORK (CAN) INTERFACE
The ADSP-BF539/ADSP-BF539F processors provide a CAN
controller that is a communication controller implementing the
controller area network (CAN) V2.0B protocol. This protocol is
an asynchronous communications protocol used in both indus-
trial and automotive control systems. CAN is well suited for
control applications due to its ability to communicate reliably
over a network since the protocol incorporates CRC checking,
message error tracking, and fault node confinement.
The CAN controller is based on a 32-entry mailbox RAM and
supports both the standard and extended identifier (ID) mes-
sage formats specified in the CAN protocol specification,
Revision 2.0, Part B.
Each mailbox consists of eight 16-bit data words. The data is
divided into fields, which includes a message identifier, a time
stamp, a byte count, up to 8 bytes of data, and several control
bits. Each node monitors the messages being passed on the net-
work. If the identifier in the transmitted message matches an
identifier in one of its mailboxes, then the module knows that
the message was meant for it, passes the data into its appropriate
mailbox, and signals the processor of message arrival with an
interrupt.
The CAN controller can wake up the ADSP-BF539/ADSP-
BF539F processors from sleep mode upon generation of a wake-
up event, such that the processor can be maintained in a low
power mode during idle conditions. Additionally, a CAN wake-
up event can wake up the on-chip internal voltage regulator
from the hibernate state.
The electrical characteristics of each network connection are
very stringent; therefore, the CAN interface is typically divided
into two parts: a controller and a transceiver. This allows a sin-
gle controller to support different drivers and CAN networks.
The ADSP-BF539/ADSP-BF539F CAN module represents the
controller part of the interface. This module’s network I/O is a
single transmit output and a single receive input, which connect
to a line transceiver.
The CAN clock is derived from the processor system clock
(SCLK) through a programmable divider and therefore does not
require an additional crystal.
ADSP-BF539/ADSP-BF539F
MEDIA TRANSCEIVER MAC LAYER (MXVR)
The ADSP-BF539/ADSP-BF539F processors provide a media
transceiver (MXVR) MAC layer, allowing the processor to be
connected directly to a MOST network through just an FOT or
electrical PHY.
The MXVR is fully compatible with the industry standard
standalone MOST controller devices, supporting 22.579 Mbps
or 24.576 Mbps data transfer. It offers faster lock times, greater
jitter immunity, a sophisticated DMA scheme for data transfers,
and the high speed internal interface to the core and L1 memory
allows the full bandwidth of the network to be utilized. The
MXVR can operate as either the network master or as a
network slave.
Synchronous data is transferred to or from the synchronous
data channels through eight programmable DMA engines. The
synchronous data DMA engines can operate in various modes,
including modes that trigger DMA operation when data pat-
terns are detected in the receive data stream. Furthermore, two
DMA engines support asynchronous traffic and a further sup-
port control message traffic.
Interrupts are generated when a user-defined amount of syn-
chronous data has been sent or received by the processor or
when asynchronous packets or control messages have been sent
or received.
The MXVR peripheral can wake up the ADSP-BF539/ADSP-
BF539F processors from sleep mode when a wake-up preamble
is received over the network or based on any other MXVR inter-
rupt event. Additionally, detection of network activity by the
MXVR can be used to wake up the ADSP-BF539/ADSP-BF539F
processors from sleep mode and wake up the on-chip internal
voltage regulator from the powered-down hibernate state. These
features allow the ADSP-BF539/ADSP-BF539F to operate in a
low-power state when there is no network activity or when data
is not currently being received or transmitted by the MXVR.
The MXVR clock is provided through a dedicated external crys-
tal or crystal oscillator. For 44.1 kHz frame syncs, use a
45.1584 MHz crystal or oscillator; for 48 kHz frame syncs, use a
49.152 MHz crystal or oscillator. If using a crystal to provide the
MXVR clock, use a parallel-resonant, fundamental mode,
microprocessor-grade crystal.
DYNAMIC POWER MANAGEMENT
The ADSP-BF539/ADSP-BF539F processors provide four oper-
ating modes, each with a different performance/power profile.
In addition, dynamic power management provides the control
functions to dynamically alter the processor core supply voltage,
further reducing power dissipation. Control of clocking to each
of the ADSP-BF539/ADSP-BF539F processor peripherals also
reduces power consumption. See Table 5 for a summary of the
power settings for each mode.
Rev. A | Page 13 of 60 | February 2008
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