ADSP-BF539(RevA) 데이터 시트보기 (PDF) - Analog Devices
부품명
상세내역
제조사
ADSP-BF539 Datasheet PDF : 60 Pages
| |||
ADSP-BF539/ADSP-BF539F
Full-On Operating Mode—Maximum Performance
In the full-on mode, the PLL is enabled and is not bypassed,
providing capability for maximum operational frequency. This
is the power-up default execution state in which maximum per-
formance can be achieved. The processor core and all enabled
peripherals run at full speed.
Active Operating Mode—Moderate Power Savings
In the active mode, the PLL is enabled but bypassed. Because the
PLL is bypassed, the processor’s core clock (CCLK) and system
clock (SCLK) run at the input clock (CLKIN) frequency. In this
mode, the CLKIN to CCLK multiplier ratio can be changed,
although the changes are not realized until the full-on mode is
entered. DMA access is available to appropriately configured L1
memories.
In the active mode, it is possible to disable the PLL through the
PLL Control register (PLL_CTL). If disabled, the PLL must be
re-enabled before transitioning to the full-on or sleep modes.
Table 5. Power Settings
Full-On Enabled
No
Active
Enabled/ disabled Yes
Sleep
Enabled
Deep Sleep Disabled
Hibernate Disabled
Enabled Enabled On
Enabled Enabled On
Disabled Enabled On
Disabled Disabled On
Disabled Disabled Off
Sleep Operating Mode—High Dynamic Power Savings
The sleep mode reduces dynamic power dissipation by disabling
the clock to the processor core (CCLK). The PLL and system
clock (SCLK), however, continue to operate in this mode. Typi-
cally an external event or RTC activity will wake up the
processor. When in the sleep mode, assertion of wake-up will
cause the processor to sense the value of the BYPASS bit in the
PLL Control register (PLL_CTL). If Bypass is disabled, the pro-
cessor will transition to the full-on mode. If Bypass is enabled,
the processor will transition to the active mode. When in the
sleep mode, system DMA access to L1 memory is not supported.
Deep Sleep Operating Mode—Maximum Dynamic Power
Savings
The deep sleep mode maximizes dynamic power savings by dis-
abling the clocks to the processor core (CCLK) and to all
synchronous peripherals (SCLK). Asynchronous peripherals
such as the RTC may still be running but will not be able to
access internal resources or external memory. This powered-
down mode can only be exited by assertion of the reset interrupt
(RESET) or by an asynchronous interrupt generated by the
RTC. When in deep sleep mode, an RTC asynchronous
interrupt causes the processor to transition to the active mode.
Assertion of RESET while in deep sleep mode causes the proces-
sor to transition to the full-on mode.
Hibernate State—Maximum Static Power Savings
The hibernate state maximizes static power savings by disabling
the voltage and clocks to the processor core (CCLK) and to all
the synchronous peripherals (SCLK). The internal voltage regu-
lator for the processor can be shut off by writing b#00 to the
FREQ bits of the VR_CTL register. This disables both CCLK
and SCLK. Furthermore, it sets the internal power supply volt-
age (VDDINT) to 0 V to provide the lowest static power
dissipation. Any critical information stored internally (memory
contents, register contents, etc.) must be written to a nonvolatile
storage device prior to removing power if the processor state is
to be preserved. Since VDDEXT is still supplied in this mode, all of
the external pins three-state, unless otherwise specified. This
allows other devices that can be connected to the processor to
have power still applied without drawing unwanted current.
The internal supply regulator can be woken up either by a real-
time clock wake-up, by CAN bus traffic, by asserting the RESET
pin, or by MOST bus traffic causing the MRXON pin to assert.
If either CAN or MXVR is not used, a general-purpose wake-up
is possible.
Power Savings
As shown in Table 6, the ADSP-BF539/ADSP-BF539F proces-
sors support five different power domains. The use of multiple
power domains maximizes flexibility, while maintaining com-
pliance with industry standards and conventions:
• The 3.3 V VDDRTC power domain supplies the RTC I/O and
logic so that the RTC can remain functional when the rest
of the chip is powered off.
• The 3.3 V MXEVDD power domain supplies the MXVR
crystal and is separate to provide noise isolation.
• The 1.25 V MPIVDD power domain supplies the MXVR
PLL and is separate to provide noise isolation.
• The 1.25 V VDDINT power domain supplies all internal logic
except for the RTC logic and the MXVR PLL.
• The 3.3 V VDDEXT power domain supplies all I/O except for
the RTC and MXVR crystals.
There are no sequencing requirements for the various power
domains.
Table 6. Power Domains
Power Domain
RTC Crystal I/O and Logic
MXVR Crystal I/O
MXVR PLL Analog and Logic
All Internal Logic Except RTC and MXVR PLL
All I/O Except RTC and MXVR Crystals
VDD Range
VDDRTC
MXEVDD
MPIVDD
VDDINT
VDDEXT
Rev. A | Page 14 of 60 | February 2008
Share Link: 