ADSP-BF539(RevA) 데이터 시트보기 (PDF) - Analog Devices
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ADSP-BF539 Datasheet PDF : 60 Pages
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ADSP-BF539/ADSP-BF539F
ADDRESS ARITHMETIC UNIT
DA1 32
DA0 32
I3 L3 B3
M3
I2 L2 B2
M2
I1 L1 B1
M1
I0 L0 B0
M0
32
RAB
DAG1
DAG0
SP
FP
P5
P4
P3
P2
P1
P0
32
PREG
SD
32
LD1
32
LD0
32
32
32
R7.H R7.L
R6.H R6.L
R5.H R5.L
R4.H R4.L
16
8
R3.H R3.L
8
8
R2.H R2.L
R1.H R1.L
BARREL
R0.H R0.L
SHIFTER
40
A0
40 40
32
32
DATA ARITHMETIC UNIT
ASTAT
16
8
40
A1
SEQUENCER
ALIGN
DECODE
LOOP BUFFER
CONTROL
UNIT
Figure 2. Blackfin Processor Core
Internal (On-Chip) Memory
The ADSP-BF539/ADSP-BF539F processor has three blocks of
on-chip memory providing high bandwidth access to the core.
The first is the L1 instruction memory, consisting of 80K bytes
SRAM, of which 16K bytes can be configured as a four-way set-
associative cache. This memory is accessed at full
processor speed.
The second on-chip memory block is the L1 data memory, con-
sisting of two banks of up to 32K bytes each. Each memory bank
is configurable, offering both cache and SRAM functionality.
This memory block is accessed at full processor speed.
The third memory block is a 4K byte scratch pad SRAM which
runs at the same speed as the L1 memories, but is only accessible
as data SRAM and cannot be configured as cache memory.
External (Off-Chip) Memory
External memory is accessed via the EBIU. This 16-bit interface
provides a glueless connection to a bank of synchronous DRAM
(SDRAM) as well as up to four banks of asynchronous memory
devices including flash, EPROM, ROM, SRAM, and memory
mapped I/O devices.
The PC133-compliant SDRAM controller can be programmed
to interface to up to 512M bytes of SDRAM. The SDRAM con-
troller allows one row to be open for each internal SDRAM
bank, for up to four internal SDRAM banks, improving overall
system performance.
The asynchronous memory controller can be programmed to
control up to four banks of devices with very flexible timing
parameters for a wide variety of devices. Each bank occupies a
1M byte segment regardless of the size of the devices used, so
that these banks will only be contiguous if each is fully popu-
lated with 1M byte of memory.
Flash Memory (ADSP-BF539F Only)
The ADSP-BF539F4 and ADSP-BF539F8 processors contain a
separate flash die, connected to the EBIU bus, within the pack-
age of the ADSP-BF539F processors. Figure 4 shows how the
flash memory die and Blackfin processor die are connected.
Rev. A | Page 5 of 60 | February 2008
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