ADSP-BF539WBBCZ5F4 데이터 시트보기 (PDF) - Analog Devices

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ADSP-BF539WBBCZ5F4

Blackfin® Embedded Processor

Analog Devices 

ADSP-BF539/ADSP-BF539F

TABLE OF CONTENTS

General Description ................................................. 4

Low Power Architecture ......................................... 4

System Integration ................................................ 4

ADSP-BF539/ADSP-BF539F Processor Peripherals ....... 4

Blackfin Processor Core .......................................... 5

Memory Architecture ............................................ 5

DMA Controllers ................................................ 10

Real Time Clock ................................................. 10

Watchdog Timer ................................................ 11

Timers ............................................................. 11

Serial Ports (SPORTs) .......................................... 11

Serial Peripheral Interface (SPI) Ports ...................... 11

Two Wire Interface ............................................. 12

UART Port ........................................................ 12

Programmable I/O Pins ........................................ 12

Parallel Peripheral Interface ................................... 13

Controller Area Network (CAN) Interface ................ 14

Media Transceiver MAC layer (MXVR) ................... 14

Dynamic Power Management ................................ 15

Voltage Regulation .............................................. 16

Clock Signals ..................................................... 16

Booting Modes ................................................... 17

Instruction Set Description ................................... 18

Development Tools ............................................. 18

Designing an Emulator Compatible Processor Board ... 19

Example Connections and Layout Considerations ...... 19

Voltage Regulator Layout Guidelines ....................... 19

MXVR Board Layout Guidelines ............................ 19

Pin Descriptions .................................................... 22

Specifications ........................................................ 27

Recommended Operating Conditions ...................... 27

Recommended Operating Conditions

—Applies to 5V Tolerant pins ............................. 27

Preliminary Technical Data

Electrical Characteristics ....................................... 27

Absolute Maximum Ratings ................................... 28

Package Information ............................................ 28

ESD Sensitivity ................................................... 28

Timing Specifications ........................................... 29

Clock and Reset Timing ..................................... 30

Asynchronous Memory Read Cycle Timing ............ 31

Asynchronous Memory Write Cycle Timing ........... 35

SDRAM Interface Timing .................................. 37

External Port Bus Request and Grant Cycle Timing .. 38

Parallel Peripheral Interface Timing ...................... 41

Serial Ports Timing ........................................... 44

Serial Peripheral Interface (SPI) Port

—Master Timing ........................................... 48

Serial Peripheral Interface (SPI) Port

—Slave Timing ............................................. 49

Universal Asynchronous Receiver-Transmitter

(UART) Port Timing ..................................... 50

Programmable Flags Cycle Timing ....................... 51

Timer Cycle Timing .......................................... 52

JTAG Test And Emulation Port Timing ................. 53

TWI Controller Timing ..................................... 54

MXVR Timing ................................................ 58

CAN Timing ................................................... 59

Output Drive Currents ......................................... 60

Power Dissipation ............................................... 62

Test Conditions .................................................. 62

Environmental Conditions .................................... 65

316-Ball Mini-BGA Pinout ....................................... 66

Outline Dimensions ................................................ 69

Ordering Guide ..................................................... 70

REVISION HISTORY

9/06—Revision PrF:

Revised Figure 3 ...................................................... 7

Updated Media Transceiver MAC layer (MXVR) .......... 14

Revised Power Savings ............................................ 15

Revised Figure 9 .................................................... 20

Corrected Driver Types in Pin Descriptions ................. 22

Corrected Pin Names and Functions in Pin Descriptions . 22

Replaced TBDs in

Asynchronous Memory Read Cycle Timing .................. 32

Replaced TBDs in

Asynchronous Memory Write Cycle Timing ................. 35

Replaced TBDs in

External Port Bus Request and Grant Cycle Timing ........ 38

Rev. PrF | Page 2 of 68 | September 2006

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