ADSP-BF539WBBCZ5F4 데이터 시트보기 (PDF) - Analog Devices

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ADSP-BF539WBBCZ5F4

Blackfin® Embedded Processor

Analog Devices 

ADSP-BF539/ADSP-BF539F

GENERAL DESCRIPTION

The ADSP-BF539/ADSP-BF539F processors are a members of

the Blackfin family of products, incorporating the Analog

Devices/Intel Micro Signal Architecture (MSA). Blackfin pro-

cessors combine a dual-MAC state-of-the-art signal processing

engine, the advantages of a clean, orthogonal RISC-like micro-

processor instruction set, and single-instruction, multiple-data

(SIMD) multimedia capabilities into a single instruction set

architecture.

The ADSP-BF539/ADSP-BF539F processors are completely

code compatible with other Blackfin processors, differing only

with respect to performance, peripherals, and on-chip memory.

Specific performance, peripherals, and memory configurations

are shown in Table 1 on Page 4.

Table 1. Processor Features

ADSP-BF539 ADSP-BF539F4 ADSP-BF539F8

Maximum 500 MHz 500 MHz

500 MHz

Performance 1000 MMACs 1000 MMACs 1000 MMACs

Instruction 16K bytes 16K bytes

SRAM/Cache

16K bytes

Instruction

SRAM

64K bytes 64K bytes

64K bytes

Data

32K bytes 32K bytes

SRAM/Cache

32K bytes

Data SRAM 32K bytes 32K bytes

32K bytes

Scratchpad 4K bytes 4K bytes

4K bytes

Flash

Not

256K x 16-bit 512K x 16-bit

applicable

SPORTs

4

4

4

SPI

3

3

3

TWI

2

2

2

UARTs

3

3

3

PPI

1

1

1

CAN

1

1

1

MXVR

1

1

1

Package option 316

316

316

By integrating a rich set of industry-leading system peripherals

and memory, Blackfin processors are the platform of choice for

next generation applications that require RISC-like program-

mability, multimedia support and leading edge signal

processing in one integrated package.

LOW POWER ARCHITECTURE

Blackfin processors provide world class power management and

performance. Blackfin processors are designed in a low power

and low voltage design methodology and feature Dynamic

Power Management, the ability to vary both the voltage and fre-

quency of operation to significantly lower overall power

consumption. Varying the voltage and frequency can result in a

Preliminary Technical Data

substantial reduction in power consumption, compared with

just varying the frequency of operation. This translates into

longer battery life and lower heat dissipation.

SYSTEM INTEGRATION

The ADSP-BF539/ADSP-BF539F processor is a highly inte-

grated system-on-a-chip solution for the next generation of

industrial and automotive applications including audio and

video signal processing. By combining advanced memory con-

figurations, such as on-chip flash memory, with industry-

standard interfaces with a high performance signal processing

core, users can develop cost-effective solutions quickly without

the need for costly external components. The system peripherals

include a MOST® Network Media Transceiver (MXVR), three

UART ports, three SPI ports, four serial ports (SPORT), one

CAN interface, two Two-Wire-Interfaces (TWI), four general

purpose timers (three with PWM capability), a real-time clock, a

watchdog timer, a Parallel Peripheral Interface, general purpose

I/O, and general purpose flag pins.

ADSP-BF539/ADSP-BF539F PROCESSOR

PERIPHERALS

The ADSP-BF539/ADSP-BF539F processor contains a rich set

of peripherals connected to the core via several high bandwidth

buses, providing flexibility in system configuration as well as

excellent overall system performance (see the block diagram

on Page 1). The general purpose peripherals include functions

such as UART, Timers with PWM (Pulse Width Modulation)

and pulse measurement capability, general purpose flag I/O

pins, a Real Time Clock, and a Watchdog Timer. This set of

functions satisfies a wide variety of typical system support needs

and is augmented by the system expansion capabilities of the

device. In addition to these general purpose peripherals, the

ADSP-BF539/ADSP-BF539F processor contains high speed

serial and parallel ports for interfacing to a variety of audio,

video, and modem codec functions. An MXVR transceiver

transmits and receives audio and video data and control infor-

mation on a MOST® automotive multimedia network. A CAN

2.0B controller is provided for automotive control networks. An

interrupt controller manages interrupts from the on-chip

peripherals or external sources. And power management con-

trol functions tailor the performance and power characteristics

of the processor and system to many application scenarios.

All of the peripherals, except for general purpose I/O, CAN,

TWI, Real Time Clock, and timers, are supported by a flexible

DMA structure. There are also four separate memory DMA

controllers dedicated to data transfers between the processor's

various memory spaces, including external SDRAM and asyn-

chronous memory. Multiple on-chip buses running at up to

133 MHz provide enough bandwidth to keep the processor core

running along with activity on all of the on-chip and external

peripherals.

The ADSP-BF539/ADSP-BF539F processor includes an on-chip

voltage regulator in support of the ADSP-BF539/ADSP-BF539F

processor Dynamic Power Management capability. The voltage

Rev. PrF | Page 4 of 68 | September 2006

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