ADSP-BF518F16 데이터 시트보기 (PDF) - Analog Devices

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ADSP-BF518F16

Blackfin Embedded Processor

Analog Devices 

ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16

(EVT), and lists their priorities are described in the

ADSP-BF51x Blackfin Processor Hardware Reference Manual

“System Interrupts” chapter.

System Interrupt Controller (SIC)

The system interrupt controller provides the mapping and rout-

ing of events from the many peripheral interrupt sources to the

prioritized general-purpose interrupt inputs of the CEC.

Although the processors provide a default mapping, the user

can alter the mappings and priorities of interrupt events by

writing the appropriate values into the interrupt assignment

registers (SIC_IARx). See the ADSP-BF51x Blackfin Processor

Hardware Reference Manual “System Interrupts” chapter for the

inputs into the SIC and the default mappings into the CEC.

The SIC allows further control of event processing by providing

three pairs of 32-bit interrupt control and status registers. Each

register contains a bit corresponding to each of the peripheral

interrupt events. For more information, see the ADSP-BF51x

Blackfin Processor Hardware Reference Manual “System Inter-

rupts” chapter.

DMA CONTROLLERS

The ADSP-BF51x processors have multiple independent DMA

channels that support automated data transfers with minimal

overhead for the processor core. DMA transfers can occur

between the processor's internal memories and any of its DMA-

capable peripherals. Additionally, DMA transfers can be accom-

plished between any of the DMA-capable peripherals and

external devices connected to the external memory interfaces,

including the SDRAM controller and the asynchronous mem-

ory controller. DMA-capable peripherals include the Ethernet

MAC, RSI, SPORTs, SPIs, UARTs, and PPI. Each individual

DMA-capable peripheral has at least one dedicated DMA

channel.

The processors’ DMA controller supports both one-dimen-

sional (1-D) and two-dimensional (2-D) DMA transfers. DMA

transfer initialization can be implemented from registers or

from sets of parameters called descriptor blocks.

The 2-D DMA capability supports arbitrary row and column

sizes up to 64K elements by 64K elements, and arbitrary row

and column step sizes up to ±32K elements. Furthermore, the

column step size can be less than the row step size, allowing

implementation of interleaved data streams. This feature is

especially useful in video applications where data can be de-

interleaved on the fly.

Examples of DMA types supported by the DMA controller

include:

• A single, linear buffer that stops upon completion

• A circular, auto-refreshing buffer that interrupts on each

full or fractionally full buffer

• 1-D or 2-D DMA using a linked list of descriptors

• 2-D DMA using an array of descriptors, specifying only the

base DMA address within a common page

In addition to the dedicated peripheral DMA channels, there are

two memory DMA channels that transfer data between the vari-

ous memories of the processor system. This enables transfers of

blocks of data between any of the memories—including external

SDRAM, ROM, SRAM, and flash memory—with minimal

processor intervention. Memory DMA transfers can be con-

trolled by a very flexible descriptor-based methodology or by a

standard register-based autobuffer mechanism.

The processors also have an external DMA controller capability

via dual external DMA request signals when used in conjunc-

tion with the external bus interface unit (EBIU). This

functionality can be used when a high speed interface is

required for external FIFOs and high bandwidth communica-

tions peripherals. It allows control of the number of data

transfers for memory DMA. The number of transfers per edge is

programmable. This feature can be programmed to allow mem-

ory DMA to have an increased priority on the external bus

relative to the core.

PROCESSOR PERIPHERALS

The ADSP-BF51x processors contain a rich set of peripherals

connected to the core via several high bandwidth buses, provid-

ing flexibility in system configuration as well as excellent overall

system performance (see Figure 2). The processors contain ded-

icated network communication modules and high speed serial

and parallel ports, an interrupt controller for flexible manage-

ment of interrupts from the on-chip peripherals or external

sources, and power management control functions to tailor the

performance and power characteristics of the processor and sys-

tem to many application scenarios.

All of the peripherals, except for the general-purpose I/O, rotary

counter, TWI, three-phase PWM, real-time clock, and timers,

are supported by a flexible DMA structure. There are also sepa-

rate memory DMA channels dedicated to data transfers

between the processor's various memory spaces, including

external SDRAM and asynchronous memory. Multiple on-chip

buses provide enough bandwidth to keep the processor core

running along with activity on all of the on-chip and external

peripherals.

Real-Time Clock

The real-time clock (RTC) provides a robust set of digital watch

features, including current time, stopwatch, and alarm. The

RTC is clocked by a 32.768 kHz crystal external to the proces-

sors. The RTC peripheral has a dedicated power supply so that it

can remain powered up and clocked even when the rest of the

processor is in a low power state. The RTC provides several pro-

grammable interrupt options, including interrupt per second,

minute, hour, or day clock ticks, interrupt on programmable

stopwatch countdown, or interrupt at a programmed alarm

time.

The 32.768 kHz input clock frequency is divided down to a 1 Hz

signal by a prescaler. The counter function of the timer consists

of four counters: a 60-second counter, a 60-minute counter, a

24-hour counter, and an 32,768-day counter.

Rev. D | Page 8 of 68 | April 2014

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