ADSP-TS101S(RevA) 데이터 시트보기 (PDF) - Analog Devices
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ADSP-TS101S Datasheet PDF : 44 Pages
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ADSP-TS101S
• Shifter—The 64-bit shifter performs logical and arith-
metic shifts, bit and bit stream manipulation, and field
deposit and extraction operations.
• Accelerator—128-bit unit for Trellis Decoding (for
example, Viterbi and Turbo decoders) and complex cor-
relations for communication applications.
Using these features, the compute blocks can:
• Provide 8 MACs per cycle peak and 7.1 MACs per cycle
sustained 16-bit performance and provide 2 MACs per
cycle peak and 1.8 MACs per cycle sustained 32-bit per-
formance (based on FIR)
• Execute six single precision floating-point or execute
twenty-four 16-bit fixed-point operations per cycle,
providing 1800 MFLOPS or 7.3 GOPS performance
• Perform two complex 16-bit MACs per cycle
• Execute eight Trellis butterflies in one cycle
Data Alignment Buffer (DAB)
The DAB is a quad word FIFO that enables loading of quad word
data from nonaligned addresses. Normally, load instructions
must be aligned to their data size so that quad words are loaded
from a quad aligned address. Using the DAB significantly
improves the efficiency of some applications, such as FIR filters.
Dual Integer ALUs (IALUs)
The ADSP-TS101S has two IALUs that provide powerful
address generation capabilities and perform many general-
purpose integer operations. Each of the IALUs:
• Provides memory addresses for data and update pointers
• Supports circular buffering and bit-reverse addressing
• Performs general-purpose integer operations, increasing
programming flexibility
• Includes a 31-word register file for each IALU
As address generators, the IALUs perform immediate or indirect
(pre- and post-modify) addressing. They perform modulus and
bit-reverse operations with no constraints placed on memory
addresses for the modulus data buffer placement. Each IALU can
specify either a single, dual, or quad word access from memory.
The IALUs have hardware support for circular buffers, bit
reverse, and zero-overhead looping. Circular buffers facilitate
efficient programming of delay lines and other data structures
required in digital signal processing, and they are commonly used
in digital filters and Fourier transforms. Each IALU provides
registers for four circular buffers, so applications can set up a total
of eight circular buffers. The IALUs handle address pointer
wraparound automatically, reducing overhead, increasing perfor-
mance, and simplifying implementation. Circular buffers can
start and end at any memory location.
Because the IALU’s computational pipeline is one cycle deep, in
most cases integer results are available in the next cycle.
Hardware (register dependency check) causes a stall if a result is
unavailable in a given cycle.
Program Sequencer
The ADSP-TS101S processor’s program sequencer supports:
• A fully interruptible programming model with flexible
programming in assembly and C/C++ languages; handles
hardware interrupts with high throughput and no aborted
instruction cycles.
• An eight-cycle instruction pipeline—three-cycle fetch
pipe and five-cycle execution pipe—with computation
results available two cycles after operands are available.
• The supply of instruction fetch memory addresses; the
sequencer’s Instruction Alignment Buffer (IAB) caches
up to five fetched instruction lines waiting to execute; the
program sequencer extracts an instruction line from the
IAB and distributes it to the appropriate core component
for execution.
• The management of program structures and determina-
tion of program flow according to JUMP, CALL, RTI,
RTS instructions, loop structures, conditions, interrupts,
and software exceptions.
• Branch prediction and a 128-entry branch target buffer
(BTB) to reduce branch delays for efficient execution of
conditional and unconditional branch instructions and
zero-overhead looping; correctly predicted branches that
are taken occur with zero-to-two overhead cycles, over-
coming the three-to-six stage branch penalty.
• Compact code without the requirement to align code in
memory; the IAB handles alignment.
Interrupt Controller
The DSP supports nested and non-nested interrupts. Each
interrupt type has a register in the interrupt vector table. Also,
each has a bit in both the interrupt latch register and the interrupt
mask register. All interrupts are fixed as either level sensitive or
edge sensitive, except the IRQ3–0 hardware interrupts, which are
programmable.
The DSP distinguishes between hardware interrupts and
software exceptions, handling them differently. When a software
exception occurs, the DSP aborts all other instructions in the
instruction pipe. When a hardware interrupt occurs, the DSP
continues to execute instructions already in the instruction pipe.
Flexible Instruction Set
The 128-bit instruction line, which can contain up to four 32-bit
instructions, accommodates a variety of parallel operations for
concise programming. For example, one instruction line can
direct the DSP to conditionally execute a multiply, an add, and
a subtract in both computation blocks while it also branches to
another location in the program. Some key features of the instruc-
tion set include:
• Enhanced instructions for communications infrastruc-
ture to govern Trellis Decoding (for example, Viterbi
and Turbo decoders) and Despreading via complex
correlations
• Algebraic assembly language syntax
• Direct support for all DSP, imaging, and video arith-
metic types, eliminating hardware modes
–4–
REV. A
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