ADSP-TS101S(RevA) 데이터 시트보기 (PDF) - Analog Devices
부품명
상세내역
제조사
ADSP-TS101S Datasheet PDF : 44 Pages
| |||
ADSP-TS101S
• Branch prediction encoded in instruction, enables zero-
overhead loops
• Parallelism encoded in instruction line
• Conditional execution optional for all instructions
• User-defined, programmable partitioning between
program and data memory
On-Chip SRAM Memory
The ADSP-TS101S has 6M bits of on-chip SRAM memory,
divided into three blocks of 2M bits (64K words × 32 bits). Each
block—M0, M1, and M2—can store program, data, or both, so
applications can configure memory to suit specific needs. Placing
program instructions and data in different memory blocks,
however, enables the DSP to access data while performing an
instruction fetch.
The DSP’s internal and external memory (Figure 2) is organized
into a unified memory map, which defines the location (address)
of all elements in the system.
The memory map is divided into four memory areas—host space,
external memory, multiprocessor space, and internal memory—
and each memory space, except host memory, is subdivided into
smaller memory spaces.
Each internal memory block connects to one of the 128-bit wide
internal buses—block M0 to bus MD0, block M1 to bus MD1,
and block M2 to bus MD2—enabling the DSP to perform three
memory transfers in the same cycle. The DSP’s internal bus
architecture provides a total memory bandwidth of 14.4G bytes
per second, enabling the core and I/O to access eight 32-bit data
words (256 bits) and four 32-bit instructions each cycle. The
DSP’s flexible memory structure enables:
• DSP core and I/O access of different memory blocks in
the same cycle
• DSP core access of all three memory blocks in parallel—
one instruction and two data accesses
• Programmable partitioning of program and data memory
• Program access of all memory as 32-, 64-, or 128-bit
words—16-bit words with the DAB
• Complete context switch in less than 20 cycles (66 ns)
External Port (Off-Chip Memory/Peripherals Interface)
The ADSP-TS101S processor’s external port provides the pro-
cessor’s interface to off-chip memory and peripherals. The
4G word address space is included in the DSP’s unified address
space. The separate on-chip buses—three 128-bit data buses and
three 32-bit address buses—are multiplexed at the external port
to create an external system bus with a single 64-bit data bus and
a single 32-bit address bus. The external port supports data
transfer rates of 800M bytes per second over external bus.
The external bus can be configured for 32- or 64-bit operation.
When the system bus is configured for 64-bit operation, the lower
32 bits of the external data bus connect to even addresses, and
the upper 32 bits connect to odd addresses.
The external port supports pipelined, slow, and SDRAM proto-
cols. Addressing of external memory devices and memory
mapped peripherals is facilitated by on-chip decoding of high
order address lines to generate memory bank select signals.
The ADSP-TS101S provides programmable memory, pipeline
depth, and idle cycle for synchronous accesses, and external
acknowledge controls to support interfacing to pipelined or slow
devices, host processors, and other memory-mapped peripherals
with variable access, hold, and disable time requirements.
Host Interface
The ADSP-TS101S provides an easy and configurable interface
between its external bus and host processors through the external
port. To accommodate a variety of host processors, the host
interface supports pipelined or slow protocols for accesses of the
host as slave. Each protocol has programmable transmission
parameters, such as idle cycles, pipe depth, and internal
wait cycles.
The host interface supports burst transactions initiated by a host
processor. After the host issues the starting address of the burst
and asserts the BRST signal, the DSP increments the address
internally while the host continues to assert BRST.
The host interface provides a deadlock recovery mechanism that
enables a host to recover from deadlock situations involving the
DSP. The BOFF signal provides the deadlock recovery mecha-
nism. When the host asserts BOFF, the DSP backs off the current
transaction and asserts HBG and relinquishes the external bus.
The host can directly read or write the internal memory of the
ADSP-TS101S, and it can access most of the DSP registers,
including DMA control (TCB) registers. Vector interrupts
support efficient execution of host commands.
Multiprocessor Interface
The ADSP-TS101S offers powerful features tailored to multi-
processing DSP systems through the external port and link ports.
This multiprocessing capability provides highest bandwidth for
interprocessor communication, including:
• Up to eight DSPs on a common bus
• On-chip arbitration for glueless multiprocessing
• Link ports for point-to-point communication
The external port and link ports provide integrated, glueless mul-
tiprocessing support.
The external port supports a unified address space (see Figure 2)
that enables direct interprocessor accesses of each ADSP-
TS101S processor’s internal memory and registers. The DSP’s
on-chip distributed bus arbitration logic provides simple, glueless
connection for systems containing up to eight ADSP-TS101S
processors and a host processor. Bus arbitration has a rotating
priority. Bus lock supports indivisible read-modify-write
sequences for semaphores. A bus fairness feature prevents one
DSP from holding the external bus too long.
The DSP’s four link ports provide a second path for interproces-
sor communications with throughput of 1G bytes per second.
The cluster bus provides 800M bytes per second throughput—
with a total of 1.8G bytes per second interprocessor bandwidth.
REV. A
–5–
Share Link: 