ADSP-TS101S(RevA) 데이터 시트보기 (PDF) - Analog Devices
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ADSP-TS101S Datasheet PDF : 44 Pages
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ADSP-TS101S
GLOBAL SPACE
0x FFFFFFFF
HOST
(MSH)
INTERNAL SPACE
0x 003 FFFFF
BANK 1
(MS1)
0 x1 00 000 00
0 x0 03 00 00 0
BANK 0
(MS0)
0 x0 C00 00 00
RE SERVE D
0 x0 02 80 00 0
SDRAM
(MSSD)
0 x0 80 000 00
0 x0 02 00 00 0
INTERNAL REGISTERS (UREGS)
RE SERVE D
INTERNAL MEMORY 2
RE SERVE D
INTERNAL MEMORY 1
RE SERVE D
INTERNAL MEMORY 0
0x 001 80 7FF
0 x0 01 80 00 0
0 x0 01 0FFFF
0 x0 01 00 00 0
0 x0 00 8FFFF
0 x0 00 80 00 0
0 x0 00 0FFFF
0 x0 00 00 00 0
PROCESSOR ID 7
PROCESSOR ID 6
PROCESSOR ID 5
PROCESSOR ID 4
PROCESSOR ID 3
PROCESSOR ID 2
PROCESSOR ID 1
PROCESSOR ID 0
BROADCAST
RES ERV ED
INTERNAL MEMORY
0 x0 40 000 00
0 x0 3C0 00 00
0 x0 38 000 00
0 x0 34 000 00
0 x0 30 000 00
0 x0 2C0 00 00
0 x0 28 000 00
0 x0 24 000 00
0 x0 20 000 00
0 x0 1C0 00 00
EACH IS A COPY
OF INTERNAL SPACE
0 x0 03 FFFFF
0 x0 00 000 00
Figure 2. Memory Map
SDRAM Controller
The SDRAM controller controls the ADSP-TS101S processor’s
transfers of data to and from synchronous DRAM (SDRAM).
The throughput is 32 or 64 bits per SCLK cycle using the external
port and SDRAM control pins.
The SDRAM interface provides a glueless interface with
standard SDRAMs—16M bit, 64M bit, 128M bit, and
256M bit. The DSP directly supports a maximum of
64M words × 32 bit of SDRAM. The SDRAM interface is
mapped in external memory in the DSP’s unified memory map.
EPROM Interface
The ADSP-TS101S can be configured to boot from external
8-bit EPROM at reset through the external port. An automatic
process (which follows reset) loads a program from the EPROM
into internal memory. This process uses 16 wait cycles for each
read access. During booting, the BMS pin functions as the
EPROM chip select signal. The EPROM boot procedure uses
DMA channel 0, which packs the bytes into 32-bit instructions.
Applications can also access the EPROM (write flash memories)
during normal operation through DMA.
The EPROM or Flash Memory interface is not mapped in the
DSP’s unified memory map. It is a byte address space limited to
a maximum of 16M bytes (24 address bits). The EPROM or
Flash Memory interface can be used after boot via a DMA.
DMA Controller
The ADSP-TS101S processor’s on-chip DMA controller, with
14 DMA channels, provides zero-overhead data transfers without
processor intervention. The DMA controller operates indepen-
dently and invisibly to the DSP’s core, enabling DMA operations
–6–
REV. A
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