ADSP-TS101S(RevA) 데이터 시트보기 (PDF) - Analog Devices
부품명
상세내역
제조사
ADSP-TS101S Datasheet PDF : 44 Pages
| |||
ADSP-TS101S
001
000
RESET
CLOCK
REFERENCE
VOLTAGE
LINK
DEVICES
(4 MAX)
(OPTIONAL)
ADSP-TS101 #7
ADSP-TS101 #6
ADSP-TS101 #5
ADSP-TS101 #4
ADSP-TS101 #3
ADSP-TS101 #2
ADSP-TS101 #1
ID2–0
RESET
CLKS/REFS
BR7–2,0
BR1
ADDR31–0
DATA63–0
LINK
CONTROL
ADSP-TS101 #0
ID2–0
BR7–1
BR0
RESET
ADDR31–0
CLKS/REFS DATA63–0
RD
WRH/L
SCLK_P
LCLK_P
ACK
MS1–0
BUSLOCK
BMS
S/LCLK_N
VREF
LCLKRAT2–0
SCLKFREQ
CPA
DPA
BOFF
DMAR3–0
BRST
IRQ3–0
FLAG3–0
LINK
HBR
HBG
MSH
FLYBY
IOEN
LXDAT7–0
LXCLKIN
LXCLKOUT
LXDIR
TMR0E
BM
CONTROLIMP2–0
DS2–0
MSSD
RAS
CAS
LDQM
HDQM
SDWE
SDCKE
SDA10
CONTROL
ADDR
DATA
OE
GLOBAL
MEMORY
AND
WE PERIPHERALS
ACK (OPTIONAL)
CS
CS
ADDR
DATA
BOOT
EPROM
(OPTIONAL)
CLOCK
ADDR
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
DATA
CS
RAS
CAS
SDRAM
MEMORY
(OPTIONAL)
DQM
WE
CKE
A10
ADDR
DATA
CLK
Figure 3. Shared Memory Multiprocessing System
to occur while the DSP’s core continues to execute program
instructions. The DMA controller performs DMA transfers
between:
• Internal memory and external memory and memory-
mapped peripherals
• Internal memory of other DSPs on a common bus, a host
processor, or link port I/O
• External memory and external peripherals or link port I/O
• External bus master and internal memory or link port I/O
The DMA controller provides a number of additional features.
The DMA controller supports Flyby transfers. Flyby operations
only occur through the external port (DMA channel 0) and do
not involve the DSP’s core. The DMA controller acts as a conduit
to transfer data from one external device to another through
external memory. During a transaction, the DSP:
• Relinquishes the external data bus
• Outputs addresses, memory selects (MS1–0, MSSD,
RAS, CAS, and SDWE) and the FLYBY, IOEN, and
RD/WR strobes
• Responds to ACK
DMA chaining is also supported by the DMA controller. DMA
chaining operations enable applications to automatically link one
DMA transfer sequence to another for continuous transmission.
The sequences can occur over different DMA channels and have
different transmission attributes.
REV. A
–7–
Share Link: 