ADSP-TS101SAB2-100 데이터 시트보기 (PDF) - Analog Devices

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ADSP-TS101SAB2-100

TigerSHARC Embedded Processor

Analog Devices 

ADSP-TS101S

PIN FUNCTION DESCRIPTIONS

While most of the ADSP-TS101S processor’s input pins are nor-

mally synchronous—tied to a specific clock—a few are

asynchronous. For these asynchronous signals, an on-chip syn-

chronization circuit prevents metastability problems. The

synchronous ac specification for asynchronous signals is used

only when predictable cycle-by-cycle behavior is required.

All inputs are sampled by a clock reference, therefore input

specifications (asynchronous minimum pulse widths or syn-

chronous input setup and hold) must be met to guarantee

recognition.

PIN STATES AT RESET

The output pins can be three-stated during normal operation.

The DSP three-states all outputs during reset, allowing these

pins to get to their internal pull-up or pull-down state. Some

output pins (control signals) have a pull-up or pull-down that

maintains a known value during transitions between different

drivers.

PIN DEFINITIONS

The Type column in the following pin definitions tables

describes the pin type, when the pin is used in the system. The

Term (for termination) column describes the pin termination

type if the pin is not used by the system. Note that some pins are

always used (indicated with au symbol).

Table 3. Pin Definitions—Clocks and Reset

Signal

Type

Term Description

LCLK_N

LCLK_P

LCLKRAT2–01

I

I

I (pd2)

au

Local Clock Reference. Connect this pin to VREF as shown in Figure 6.

au

Local Clock Input. DSP clock input. The instruction cycle rate = n  LCLK, where n is user-

programmable to 2, 2.5, 3, 3.5, 4, 5, or 6. For more information, see Clock Domains on Page 9.

au

LCLK Ratio. The DSP’s core clock (instruction cycle rate) = n  LCLK, where n is user-program-

mable to 2, 2.5, 3, 3.5, 4, 5, or 6 as shown in Table 4. These pins must have a constant value while

the DSP is powered.

SCLK_N

I

au

System Clock Reference. Connect this pin to VREF as shown in Figure 6.

SCLK_P

I

au

System Clock Input. The DSP’s system input clock for cluster bus. This pin must be connected

to the same clock source as LCLK_P. For more information, see Clock Domains on Page 9.

SCLKFREQ3

I (pu2)

au

SCLK Frequency. SCLKFREQ = 1 is required. The SCLKFREQ pin must have a constant value while

the DSP is powered.

RESET

I/A

au

Reset. Sets the DSP to a known state and causes program to be in idle state. RESET must be

asserted at specified time according to the type of reset operation. For details, see Reset and

Booting on Page 9.

Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply;

pd = internal pull-down approximately 100 k; pu = internal pull-up approximately 100 k; T = three-state

Term (for termination) column symbols: epd = external pull-down approximately 10 k to VSS; epu = external pull-up approximately 10 k

to VDD-IO, nc = not connected; au = always used.

1 The internal pull-down may not be sufficient. A stronger pull-down may be necessary.

2 See Electrical Characteristics on Page 20 for maximum and minimum current consumption for pull-up and pull-down resistances.

3 The internal pull-up may not be sufficient. A stronger pull-up may be necessary.

Table 4. LCLK Ratio

LCLKRAT2–0

000 (default)

001

010

011

100

101

110

111

Ratio

2

2.5

3

3.5

4

5

6

Reserved

Rev. C | Page 12 of 48 | May 2009

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