ADSP-TS101SAB2-100 데이터 시트보기 (PDF) - Analog Devices

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ADSP-TS101SAB2-100

TigerSHARC Embedded Processor

Analog Devices 

ADSP-TS101S

Table 15. Pin Definitions—Power, Ground, and Reference

Signal

Type

Term Description

VDD

VDD_A

VDD_IO

VREF

P

au

VDD pins for internal logic.

P

au

VDD pins for analog circuits. Pay critical attention to bypassing this supply.

P

au

VDD pins for I/O buffers.

I

au

Reference voltage defines the trip point for all input buffers, except RESET, IRQ3–0, DMAR3–0,

ID2–0, CONTROLIMP2–0, TCK, TDI, TMS, and TRST. The value is 1.5 V ± 100 mV (which is the TTL

trip point). VREF can be connected to a power supply or set by a voltage divider circuit. The

voltage divider should have an HF decoupling capacitor (1 nF HF SMD) connected to VSS. Tie

the decoupling capacitor between VREF input and VSS, as close to the DSP’s pins as possible. For

more information, see Filtering Reference Voltage and Clocks on Page 10.

VSS

G

au

Ground pins.

VSS_A

G

au

Ground pins for analog circuits.

NC

No connect. Do not connect these pins to anything (not to any supply, signal, or each other),

because they are reserved and must be left unconnected.

Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply;

pd = internal pull-down approximately 100 k; pu = internal pull-up approximately 100 k; T = three-state

Term (for termination) column symbols: epd = external pull-down approximately 10 k to VSS; epu = external pull-up approximately 10 k

to VDD-IO, nc = not connected; au = always used.

STRAP PIN FUNCTION DESCRIPTIONS

Some pins have alternate functions at reset. Strap options set

DSP operating modes. During reset, the DSP samples the strap

option pins. Strap pins have an approximately 100 k pull-

down for the default value. If a strap pin is not connected to an

external pull-up or logic load, the DSP samples the default value

during reset. If strap pins are connected to logic inputs, a stron-

ger external pull-down may be required to ensure default value

depending on leakage and/or low level input current of the logic

load. To set a mode other than the default mode, connect the

strap pin to a sufficiently stronger external pull-up. In a multi-

processor system, up to eight DSPs may be connected on the

cluster bus, resulting in parallel combination of strap pin pull-

down resistors. Table 16 lists and describes each of the DSP’s

strap pins.

Table 16. Pin Definitions—I/O Strap Pins

Signal

EBOOT

IRQEN

TM1

TM2

On Pin …

BMS

BM

L2DIR

TMR0E

Description

EPROM boot.

0 = boot from EPROM immediately after reset (default)

1 = idle after reset and wait for an external device to boot DSP through the

external port or a link port

Interrupt Enable.

0 = disable and set IRQ3–0 interrupts to level sensitive after reset (default)

1 = enable and set IRQ3–0 interrupts to edge sensitive immediately after reset

Test Mode 1.

0 = required setting during reset.

1 = reserved.

Test Mode 2.

0 = required setting during reset.

1 = reserved.

Rev. C | Page 19 of 48 | May 2009

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