ADSP-BF538F(Rev0) 데이터 시트보기 (PDF) - Analog Devices
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ADSP-BF538F Datasheet PDF : 56 Pages
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Vertical Blanking Interval Mode
In this mode, the PPI only transfers vertical blanking interval
(VBI) data.
Entire Field Mode
In this mode, the entire incoming bit stream is read in through
the PPI. This includes active video, control preamble sequences,
and ancillary data that may be embedded in horizontal and ver-
tical blanking intervals. Data transfer starts immediately after
synchronization to Field 1.
CONTROLLER AREA NETWORK (CAN) INTERFACE
The ADSP-BF538/ADSP-BF538F processors provide a CAN
controller that is a communication controller implementing the
Controller Area Network (CAN) V2.0B protocol. This protocol
is an asynchronous communications protocol used in both
industrial and automotive control systems. CAN is well suited
for control applications due to its capability to communicate
reliably over a network since the protocol incorporates CRC
checking, message error tracking, and fault node confinement.
The CAN controller is based on a 32-entry mailbox RAM and
supports both the standard and extended identifier (ID) mes-
sage formats specified in the CAN protocol specification,
revision 2.0, part B.
Each mailbox consists of eight 16-bit data words. The data is
divided into fields, which includes a message identifier, a time
stamp, a byte count, up to 8 bytes of data, and several control
bits. Each node monitors the messages being passed on the net-
work. If the identifier in the transmitted message matches an
identifier in one of its mailboxes, then the module knows that
the message was meant for it, passes the data into its appropriate
mailbox, and signals the processor of message arrival with an
interrupt.
The CAN controller can wake up the processor from sleep mode
upon generation of a wakeup event, such that the processor can
be maintained in a low power mode during idle conditions.
Additionally, a CAN wakeup event can wake up the on-chip
internal voltage regulator from the powered-down
hibernate state.
The electrical characteristics of each network connection are
very stringent, therefore the CAN interface is typically divided
into 2 parts: a controller and a transceiver. This allows a single
controller to support different drivers and CAN networks. The
ADSP-BF538/ADSP-BF538F CAN module represents the con-
troller part of the interface. This module’s network I/O is a
single transmit output and a single receive input, which connect
to a line transceiver.
The CAN clock is derived from the processor system clock
(SCLK) through a programmable divider and therefore does not
require an additional crystal.
DYNAMIC POWER MANAGEMENT
The ADSP-BF538/ADSP-BF538F processors provide four oper-
ating modes, each with a different performance/power profile.
In addition, dynamic power management provides the control
functions to dynamically alter the processor core supply voltage,
ADSP-BF538/ADSP-BF538F
further reducing power dissipation. Control of clocking to each
of the processor peripherals also reduces power consumption.
See Table 5 for a summary of the power settings for each mode.
Full-On Operating Mode—Maximum Performance
In the full-on mode, the PLL is enabled and is not bypassed,
providing capability for maximum operational frequency. This
is the powerup default execution state in which maximum per-
formance can be achieved. The processor core and all enabled
peripherals run at full speed.
Active Operating Mode—Moderate Power Savings
In the active mode, the PLL is enabled but bypassed. Because the
PLL is bypassed, the processor’s core clock (CCLK) and system
clock (SCLK) run at the input clock (CLKIN) frequency. In this
mode, the CLKIN to CCLK multiplier ratio can be changed,
although the changes are not realized until the full-on mode is
entered. DMA access is available to appropriately configured L1
memories.
In the active mode, it is possible to disable the PLL through the
PLL Control register (PLL_CTL). If disabled, the PLL must be
re-enabled before transitioning to the Full-On or Sleep modes.
Table 5. Power Settings
Full On Enabled
No
Active
Enabled/ Disabled Yes
Sleep
Enabled
Deep Sleep Disabled
Hibernate Disabled
Enabled Enabled On
Enabled Enabled On
Disabled Enabled On
Disabled Disabled On
Disabled Disabled Off
Sleep Operating Mode—High Dynamic Power Savings
The sleep mode reduces dynamic power dissipation by disabling
the clock to the processor core (CCLK). The PLL and system
clock (SCLK), however, continue to operate in this mode. Typi-
cally an external event or RTC activity will wake up the
processor. When in the Sleep mode, assertion of wakeup causes
the processor to sense the value of the BYPASS bit in the PLL
control register (PLL_CTL). If BYPASS is disabled, the proces-
sor transitions to the full on mode. If BYPASS is enabled, the
processor will transition to the Active mode. When in the sleep
mode, system DMA access to L1 memory is not supported.
Deep Sleep Operating Mode—Maximum Dynamic Power
Savings
The deep sleep mode maximizes dynamic power savings by dis-
abling the clocks to the processor core (CCLK) and to all
synchronous peripherals (SCLK). Asynchronous peripherals
such as the RTC may still be running, but will not be able to
access internal resources or external memory. This powered
down mode can only be exited by assertion of the reset interrupt
(RESET) or by an asynchronous interrupt generated by the
Rev. 0 | Page 13 of 56 | May 2007
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