ADSP-BF538F(Rev0) 데이터 시트보기 (PDF) - Analog Devices
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ADSP-BF538F Datasheet PDF : 56 Pages
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ADSP-BF538/ADSP-BF538F
RTC. When in deep sleep mode, an RTC asynchronous inter-
rupt causes the processor to transition to the active mode.
Assertion of RESET while in deep sleep mode causes the proces-
sor to transition to the full on mode after processor reset.
Hibernate State—Maximum Static Power Savings
The hibernate state maximizes static power savings by disabling
the voltage and clocks to the processor core (CCLK) and to all
the synchronous peripherals (SCLK). The internal voltage regu-
lator for the processor can be shut off by writing b#00 to the
FREQ bits of the VR_CTL register. This disables both CCLK
and SCLK. Furthermore, it sets the internal power supply volt-
age (VDDINT) to 0 V to provide the lowest static power
dissipation. Any critical information stored internally (memory
contents, register contents, etc.) must be written to a nonvolatile
storage device prior to removing power if the processor state is
to be preserved. Since VDDEXT is still supplied in this mode, all of
the external pins three-state, unless otherwise specified. This
allows other devices that may be connected to the processor to
still have power applied without drawing unwanted current.
The internal supply regulator can be woken up either by a real
time clock wakeup, by CAN bus traffic, by asserting the RESET
pin, or by an external source.
Power Savings
As shown in Table 6, the ADSP-BF538/ADSP-BF538F proces-
sors support three different power domains. The use of multiple
power domains maximizes flexibility, while maintaining com-
pliance with industry standards and conventions. The 3.3 V
VDDRTC power domain supplies the RTC I/O and logic so that
the RTC can remain functional when the rest of the chip is pow-
ered off. The 1.25 V VDDINT power domain supplies all the
internal logic except for the RTC logic. The 3.3 V VDDEXT power
domain supplies all the I/O except for the RTC crystal. There
are no sequencing requirements for the various power domains.
Table 6. Power Domains
Power Domain
RTC Crystal I/O and Logic
All Internal Logic Except RTC
All I/O Except RTC
VDD Range
VDDRTC
VDDINT
VDDEXT
The VDDRTC should either be connected to a battery (if the RTC
is to operate while the rest of the chip is powered down) or
should be connected to the VDDEXT plane on the board. The
VDDRTC should remain powered when the processor is in hiber-
nate state, and should also be powered even if the RTC
functionality is not being used in an application.
The power dissipated by a processor is largely a function of the
clock frequency of the processor and the square of the operating
voltage. For example, reducing the clock frequency by 25%
results in a 25% reduction in dynamic power dissipation, while
reducing the voltage by 25% reduces dynamic power dissipation
by more than 40%. Further, these power savings are additive, in
that if the clock frequency and supply voltage are both reduced,
the power savings can be dramatic.
The dynamic power management feature of the processor
allows both the processor’s input voltage (VDDINT) and clock fre-
quency (fCCLK) to be dynamically controlled.
The savings in power dissipation can be modeled using the
power savings factor and % power savings calculations.
The power savings factor is calculated as:
Power Savings Factor
=
-f--C---C---L--K---R--E---D--
fCCLKNOM
×
⎛
⎝
V-V--D--D-D--D-I--NI-N--T-T-N--R-O-E--M-D-⎠⎞
2
×
⎛
⎝
-T----R---E--D--
TNOM
⎞
⎠
where the variables in the equation are:
• fCCLKNOM is the nominal core clock frequency
• fCCLKRED is the reduced core clock frequency
• VDDINTNOM is the nominal internal supply voltage
• VDDINTRED is the reduced internal supply voltage
• TNOM is the duration running at fCCLKNOM
• TRED is the duration running at fCCLKRED
The power savings factor is calculated as:
% Power Savings = (1 – Power Savings Factor) × 100%
VOLTAGE REGULATION
The Blackfin processor provides an on-chip voltage regulator
that can generate processor core voltage levels of 0.8 V
(–5%/+10%) to 1.2 V (–5%/+10%) and 1.25 V (–4% to +10%)
from an external 2.7 V to 3.6 V supply. Figure 6 shows the typi-
cal external components required to complete the power
management system.
2.25V TO 3.6V
INPUT VOLTAGE
RANGE
VDDEXT
(LOW-INDUCTANCE)
SET OF DECOUPLING
CAPACITORS
100nF
+
100µF
FDS9431A
10µF
LOW ESR
+
100µF
10µH
+
100µF
ZHCS1000
SHORT AND LOW-
INDUCTANCE WIRE
NOTE: DESIGNER SHOULD MINIMIZE
TRACE LENGTH TO FDS9431A.
VDDEXT
VDDINT
VROU T
VROU T
GND
Figure 6. Voltage Regulator Circuit
Rev. 0 | Page 14 of 56 | May 2007
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